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PDF NCP3420 Data sheet ( Hoja de datos )
| Número de pieza | NCP3420 | |
| Descripción | MOSFET Driver with Dual Outputs | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NCP3420
www.DataSheet4U.com
MOSFET Driver with Dual
Outputs for Synchronous
Buck Converters
The NCP3420 is a single Phase 12 V MOSFET gate driver
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 30 ns
propagation delay and a 20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 35 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
Features
• Thermal Shutdown for System Protection
• Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
• Anti Cross−Conduction Protection Circuitry
• One Input Signal Controls Both the Upper and Lower Gate Outputs
• Output Disable Control Turns Off Both MOSFETs
• Complies with VRM10.x and VRM11.x Specifications
• Undervoltage Lockout
• Thermally Enhanced Package Available
• These are Pb−Free Devices
http://onsemi.com
8
1
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAMS
8
3420
ALYW
G
1
1
DFN8
MN SUFFIX
CASE 506BJ
18
3420
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN CONNECTIONS
BST 1
8 DRVH
IN SWN
OD PGND
VCC DRVL
18
BST
IN
OD
VCC
DRVH
SWN
PGND
DRVL
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP3420DR2G
SO−8 2500 Tape & Reel
(Pb−Free)
NCP3420MNR2G DFN8 3000 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 3
1
Publication Order Number:
NCP3420/D
1 page  
OD
DRVH
or
DRVL
IN
DRVL
DRVH−SW
SW
NCP3420
VOD_LO
tpdlOD
90%
VOD_HI
tpdhOD
10%
Figure 2. Output Disable Timing Diagram
www.DataSheet4U.com
VPWM_HI
tpdlDRVL
tfDRVL
90%
2V
10%
tpdhDRVH
trDRVH
90%
10%
VPWM_LO
90%
tpdlDRVH
tfDRVH
90%
10%
trDRVL
2V 10%
tpdhDRVL
Figure 3. Nonoverlap Timing Diagram
http://onsemi.com
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet NCP3420.PDF ] | |
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