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PDF EN25Q64 Data sheet ( Hoja de datos )
| Número de pieza | EN25Q64 | |
| Descripción | 64 Megabit Serial Flash Memory | |
| Fabricantes | Eon Silicon Solution | |
| Logotipo |  |
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EN25Q64
EN25Q64
64 Megabit Serial Flash Memory with 4Kbyte Uniform Sector
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• 64 M-bit Serial Flash
- 64 M-bit/8192 K-byte/32768 pages
- 256 bytes per programmable page
• Standard, Dual or Quad SPI
- Standard SPI: CLK, CS#, DI, DO, WP#
- Dual SPI: CLK, CS#, DQ0, DQ1, WP#
- Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
• High performance
- 104MHz clock rate for one data bit
- 50MHz clock rate for two data bits
- 50MHz clock rate for four data bits
• Low power consumption
- 12 mA typical active current
- 1 μA typical power down current
• Uniform Sector Architecture:
- 2048 sectors of 4-Kbyte
- 128 blocks of 64-Kbyte
- Any sector or block can be erased individually
• Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
• High performance program/erase speed
- Page program time: 1.3ms typical
- Sector erase time: 90ms typical
- Block erase time 500ms typical
- Chip erase time: 30 seconds typical
• Write Suspend and Write Resume
• Lockable 512 byte OTP security sector
• Minimum 100K endurance cycle
• Package Options
- 8 pins SOP 200mil body width
- 8 contact VDFN (5x6mm)
- 8 contact VDFN (6x8mm)
- 16 pins SOP 300mil body width
- All Pb-free packages are RoHS compliant
• Industrial temperature Range
GENERAL DESCRIPTION
The EN25Q64 is a 64 Megabit (8192K-byte) Serial Flash memory, with advanced write protection
mechanisms. The EN25Q64 supports the standard Serial Peripheral Interface (SPI), and a high
performance Dual output as well as Quad I/O using SPI pins: Serial Clock, Chip Select, Serial DQ0(DI),
DQ1(DO), DQ2(WP#) and DQ3(NC). SPI clock frequencies of up to 50MHz are supported allowing
equivalent clock rates of 100MHz for Dual Output and 200MHz for Quad Output when using the
Dual/Quad Output Fast Read instructions. The memory can be programmed 1 to 256 bytes at a time,
using the Page Program instruction.
The EN25Q64 is designed to allow either single Sector/Block at a time or full chip erase operation. The
EN25Q64 can be configured to protect part of the memory as the software protected mode. The device
can sustain a minimum of 100K program/erase cycles on each sector or block.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
1
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/10/19
www.eonssi.com
1 page  
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EN25Q64
MEMORY ORGANIZATION
The memory is organized as:
z 8,388,608 bytes
z Uniform Sector Architecture
128 blocks of 64-Kbyte
2048 sectors of 4-Kbyte
z 32768 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
5
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/10/19
www.eonssi.com
5 Page 
Figure 4. Quad SPI Modes
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EN25Q64
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and
a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal
Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed
at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page
of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a time,
using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or
throughout the entire memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle
(of duration tSE tBE or tCE). The Erase instruction must be preceded by a Write Enable (WREN)
instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, tBE or tCE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip
Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal
cycles have completed (Program, Erase, Write Status Register). The device then goes into the Stand-
by Power mode. The device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down
Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains
in this mode until another specific instruction (the Release from Deep Power-down Mode and Read
Device ID (RDI) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used
as an extra software protection mechanism, when the device is not in active use, to protect the device
from inadvertent Write, Program or Erase instructions.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
11
©2004 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2009/10/19
www.eonssi.com
11 Page | ||
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| PDF Descargar | [ Datasheet EN25Q64.PDF ] | |
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