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NB7L14 fiches techniques PDF

ON Semiconductor - 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer

Numéro de référence NB7L14
Description 2.5V / 3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer
Fabricant ON Semiconductor 
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NB7L14 fiche technique
NB7L14
www.DataSheet4U.com
2.5V / 3.3V 7GHz/10Gbps
Differential 1:4 LVPECL
Fanout Buffer
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L14 is a differential 1:4 LVPECL fanout buffer. The
NB7L14 produces four identical LVPECL output copies of Clock or
Data operating up to 7 GHz or 10.7 Gb/s, respectively. As such, the
NB7L14 is ideal for SONET, GigE, Fiber Channel, Backplane and
other Clock or Data distribution applications.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT Pin. This feature allows the
NB7L14 to accept various logic standards, such as LVPECL, CML,
LVDS, LVCMOS or LVTTL logic levels. The VREFAC reference
output can be used to rebias capacitorcoupled differential or
singleended input signals. The 1:4 fanout design was optimized for
low output skew applications.
The NB7L14 is a member of the GigaCommfamily of high
performance clock products.
Features
Input Data Rate > 10.7 Gb/s
Input Clock Frequency > 7 GHz
165 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
<15 ps max Output Skew
<0.8 ps maximum RMS Clock Jitter
<15 ps pp of Data Dependent Jitter
Differential LVPECL Outputs, 720 mV peaktopeak, typical
LVPECL Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
NECL Operating Range: VCC = 0 V with GND = 2.375 V to 3.6 V
Internal Input Termination Resistors, 50 W
VREFAC Reference Output
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
1
QFN16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
ÇÇÇÇ1
NB7L
14
ALYWG
G
XXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
IN
50 W
VT
50 W
IN
VREFAC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Figure 1. Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
February, 2009 Rev. 2
1
Publication Order Number:
NB7L14MD

PagesPages 9
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