|
|
PDF NB3N3002 Data sheet ( Hoja de datos )
| Número de pieza | NB3N3002 | |
| Descripción | HCSL Clock Generator | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NB3N3002 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
NB3N3002
3.3V, Crystal to 25MHz,
100MHz, 125MHz and
200MHz HCSL Clock
Generator
Description
The NB3N3002 is a precision, low phase noise clock generator that
supports PCI−Express and Ethernet requirements. The device accepts
a 25 MHz fundamental mode parallel resonant crystal and generates a
differential HCSL output at 25 MHz, 100 MHz, 125 MHz or 200 MHz
clock frequencies. Outputs can interface with LVDS with proper
termination (See Figure 5).
This device is housed in 5.0 mm x 4.4 mm narrow body TSSOP 16
pin package.
Features
• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal
• External Loop Filter is Not Required
• HCSL Differential Output or LVDS with Proper Termination
• For Selectable Multipliers of the Input Frequency
• Output Enable with Tri−State Outputs
• PCIe Gen1, Gen2, Gen3 Jitter Compliant
• Typical TIE RMS jitter of 2.5 ps
• Phase Noise: @ 100 MHz
Offset Noise Power
100 Hz −109.4 dBc
1 kHz −127.8 dBc
10 kHz −136.2 dBc
100 kHz −138.8 dBc
1 MHz −138.2 dBc
10 MHz −161.4 dBc
20 MHz −163.00 dBc
• Operating Range 3.3 V ±5%
• Industrial Temperature Range −40°C to +85°C
• These are Pb−Free Devices
http://onsemi.com
16
1
TSSOP−16
DT SUFFIX
CASE 948F
MARKING
DIAGRAM
16
NB3N
3002
ALYWG
1G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(*Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
VDD
X1/CLK
25 MHz Clock or
Crystal X2
Clock Buffer
Crystal Oscillator
Phase
Detector
BM
Charge
Pump
VCO
HSCL
Output
CLK
CLK
GND
SEL0
Figure 1. NB3N3002 Simplified Logic Diagram
SEL1 OE IREF
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 6
1
Publication Order Number:
NB3N3002/D
1 page  
NB3N3002
Table 7. AC ELECTRICAL CHARACTERISTICS − PCI EXPRESS JITTER SPECIFICATIONS,
VDD = 3.3 V ± 5%, TA = −40°C to 85°C
Symbol
Characteristic
Test Conditions
Min Typ Max
PCIe Inductry
Spec
Unit
Phase Jitter
P−P
(Notes 11
and 14)
TJ
PCIe Gen1
ƒ = 100 MHz, 25 MHz Crystal
Input
Evaluation Band: 0 Hz − Nyquist
(clock frequency/2)
6 21 86 ps
Phase Jitter
RMS
(Notes 11
and 14)
tREFCLK_HF_RMS
(PCIe Gen 2)
ƒ = 100 MHz, 25 MHz Crystal
Input
High Band: 1.5 MHz − Nyquist
(clock frequency/2)
0.6 3 3.1 ps
Phase Jitter
RMS
(Notes 11
and 14)
tREFCLK_LF_RMS
(PCIe Gen 2)
ƒ = 100 MHz, 25 MHz Crystal
Input
Low Band: 10 kHz − 1.5 MHz
0.08 0.3
3
ps
Phase Jitter
RMS
(Notes 13
and 14)
tREFCLK_RMS
(PCIe Gen 3)
ƒ = 100 MHz, 25 MHz Crystal
Input
Evaluation Band: 0 Hz − Nyquist
(clock frequency/2)
0.23 0.7
0.8
ps
10. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
11. Peak−to−Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1 is 86 ps
peak−to−peak for a sample size of 106 clock periods.
12. RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and reporting the
worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1 ps RMS for tREFCLK_HF_RMS (High Band)
and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
13. RMS jitter after applying system transfer function for the common clock architecture.
14. This parameter is guaranteed by characterization. Not tested in production
HCSL
Driver
IREF
RREF = 475 W
RL = 33.2 W
RL = 33.2 W
Zo = 50 W
Zo = 50 W
RL = 49.9 W
HCSL
Receiver
RL =
49.9 W
Figure 3. Typical Termination for Output Driver and Device Evaluation
700 mV
525 mV
525 mV
0 mV
175 mV
175 mV
tR 340 ps
340 ps
tF
Figure 4. HCSL Output Parameter Characteristics
http://onsemi.com
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet NB3N3002.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NB3N3001 | PureEdge Clock Generator | ON Semiconductor |
| NB3N3002 | HCSL Clock Generator | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |