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PDF M36L0T8060B1 Data sheet ( Hoja de datos )
| Número de pieza | M36L0T8060B1 | |
| Descripción | (M36L0T8060B1 / M36L0T8060T1) 256 Mbit Flash memory and 64 Mbit PSRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M36L0T8060T1
M36L0T8060B1
256 Mbit (16 Mb ×16, multiple bank, multilevel, burst) Flash memory
and 64 Mbit PSRAM, 1.8 V core, 3 V I/O supply, multichip package
Features
Multichip package
■ 1 die of 256 Mbit (16 Mb ×16, multiple bank,
multilevel, burst) Flash memory
■ 1 die of 64 Mbit (4 Mb ×16) Pseudo SRAM
■ Supply voltage
– VDDF = 1.7 V to 1.95 V
– VDDQF = VCCP = 2.7 V to 3.1 V
– VPPF = 9 V for fast program
■ Electronic signature
– Manufacturer code: 20h
– Top device code
M36L0T8060T1: 880Dh
– Bottom device code
M36L0T8060B1: 880Eh
■ Package
– ECOPACK®
Flash memory
■ Synchronous/asynchronous read
– Synchronous burst read mode: 52 MHz
– Asynchronous page read mode
– Random access: 85 ns
■ Synchronous burst read suspend
■ Programming time
– 5 µs typical word program time using Buffer
Enhanced Factory Program command
■ Memory organization
– Multiple bank memory array: 16 Mbit banks
– Parameter blocks (top or bottom location)
■ Dual operations
– Program/erase in one bank while read in
others
– No delay between read and write
operations
■ 100 000 program/erase cycles per block
FBGA
TFBGA88 (ZAQ)
8 x 10 mm
■ Security
– 64 bit unique device number
– 2112 bit user programmable OTP cells
■ Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WPF for block lock-down
– Absolute write protection with VPPF = VSS
■ Common Flash interface (CFI)
PSRAM
■ Access time: 65 ns
■ Low standby current: 90 µA (TA≤40 °C)
■ Deep power-down current: 10 µA
■ Byte control: UB/LB
■ Compatible with standard LPSRAM
■ Wide operating temperature
– TA = –30 to +85 °C
■ Power-down modes
– Deep power-down
February 2008
Rev 1
1/22
www.st.com
1
1 page  
M36L0T8060T1, M36L0T8060B1
List of figures
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List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TFBGA88 8 × 10 mm, 8 × 10 ball array - 0.8 mm pitch, bottom view
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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5 Page 
M36L0T8060T1, M36L0T8060B1
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Signal descriptions
2.12
PSRAM Chip Enable (E2P)
The Chip Enable, E2P, puts the device in power-down mode (deep power-down, PAR and
standby) when it is driven Low. Deep power-down mode is the lowest power mode.
It is not allowed to set EF to VIL, E1P to VIL and E2P to VIH at the same time.
2.13
PSRAM Output Enable (GP)
The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write
cycles to be achieved with the common I/O data bus.
2.14
2.15
PSRAM Write Enable (WP)
The Write Enable, WP, controls the bus write operation of the PSRAM’s command interface.
PSRAM Upper Byte Enable (UBP)
The Upper Byte Enable, UBP, gates the data on the upper byte data inputs/outputs (DQ8-
DQ15) to or from the upper part of the selected address during a write or read operation.
2.16
PSRAM Lower Byte Enable (LBP)
The Lower Byte Enable, LBP, gates the data on the lower byte data inputs/outputs (DQ0-
DQ7) to or from the lower part of the selected address during a write or read operation.
2.17
Flash VDDF supply voltage
VDDF provides the power supply to the internal core of the Flash memory. It is the main
power supply for all Flash memory operations (read, program, and erase).
2.18
PSRAM VCCP supply voltage
The VCCP supply voltage supplies the power for all PSRAM operations (read, write, etc.) and
for driving the refresh logic, even when the device is not being accessed.
2.19
Flash VDDQF supply voltage
VDDQF provides the power supply for the Flash I/O pins. This allows all outputs to be
powered independently of the Flash memory core power supply, VDDF.
11/22
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| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet M36L0T8060B1.PDF ] | |
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