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PDF 73S1210F Data sheet ( Hoja de datos )
| Número de pieza | 73S1210F | |
| Descripción | Self-Contained Smart Card Reader | |
| Fabricantes | Teridian Semiconductor | |
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73S1210F
Self-Contained Smart Card Reader
with PINpad and Power Management
Simplifying System Integration™
DATA SHEET
May 2009
GENERAL DESCRIPTION
The 73S1210F is a versatile and economical CMOS
System-on-Chip device intended for smart card reader
applications. The circuit is built around an 80515 high-
performance core; it features primarily an ISO-7816 / EMV
interface and a generic asynchronous serial interface.
Delivered with turnkey Teridian embedded firmware, it
forms a ready-to-use smart card reader solution that can be
seamlessly incorporated into any microprocessor-based
system where a serial line is available.
The solution is scalable, thanks to a built-in I2C interface
that allows to drive external electrical smart card interfaces
such as Teridian 73S8010 ICs. This makes the solution
immediately able to support multi-card slots or multi-SAM
architectures.
In addition, the 73S1210 features a 5x6 PINpad interface, 8
user I/Os, multiple interrupt options and an analog voltage
input (for DC voltage monitoring such as battery level
detection) that make it suitable for low-cost PINpad reader
devices.
The 80515 CPU core instruction set is compatible with the
industry standard 8051, while offering one clock-cycle per
instruction processing power (most instructions). With a
CPU clock running up to 24MHz, it results in up to 24MIPS
available that meets the requirements of various encryption
needs such as AES, DES / 3-DES and even RSA (for PIN
encryption for instance).
The circuit requires a single 6MHz to 12MHz crystal.
The respective 73S1210F embedded memories are 32KB
Flash program memory, 2KB user XRAM memory, and
256B IRAM memory. Dedicated FIFOs for the ISO 7816
UART are independent from the user XRAM and IRAM.
Alternatively to the turnkey firmware offered by Teridian,
customers can develop their own embedded firmware
directly within their application or using Teridian 73S1210F
Evaluation Board through a JTAG-like interface.
The chip incorporates an inductor-based DC-DC converter
that generates all the necessary voltages to the various
73S1210F function blocks (smart card interface, digital
core, etc.) from any of two distinct power supply sources:
the +5V bus (VBUS, 4.4 to 6.5V), or a main battery (VBAT,
4.0V to 6.5V). The chip automatically powers-up the DC-
DC converter with VBUS if it is present, or uses VBAT as the
supply input if VBUS is not present. Alternatively, the pin VPC
can support a wider power supply input range (2.7V to
6.5V), when using a single system supply source.
In addition, the circuit features an ON/OFF mode which
operates directly with an ON/OFF system switch: Any
activity on the ON/OFF button is debounced internally
and controls the power generation circuit accordingly,
under the supervision of the firmware (OFF request /
OFF acknowledgement at firmware level). The OFF
mode can be alternatively initiated from the controller
(firmware action instead of ON/OFF switch).
In OFF mode, the circuit typically draws less than 1µA,
which makes it ideal for applications where battery life
must be maximized.
Embedded Flash memory is in-system programmable
and lockable by means of on-silicon fuses. This makes
the 73S1210F suitable for both development and
production phases.
Teridian Semiconductor Corporation offers with its
73S1210F a very comprehensive set of software
libraries for EMV. Refer to the 73S12xxF Software
User’s Guide for a complete description of the
Application Programming Interface (API Libraries) and
related software modules.
A complete array of development and programming
tools, libraries and demonstration boards enable rapid
development and certification of readers that meet
most demanding smart card standards.
APPLICATIONS
• PINpad smart card readers:
o With serial connectivity
o Ideal for low-cost POS Terminals and Digital
Identification (Secure Login, Gov’t ID, ...)
• SIM Readers in Personal Wireless devices
• Payphones & Vending machines
• General purpose smart card readers
ADVANTAGES
• Reduced BOM
• Versatile power supply options
o 2.7V to 6.5V ranges
• Higher performance CPU core (up to 24MIPS)
• Built-in EMV/ISO slot, expandable to multi-slots
• Flexible power supply options
o On-chip DC-DC converter
o CMOS switches between supply inputs
• Sub-µA Power Down mode with ON/OFF switch
• Powerful In-Circuit Emulation and Programming
• A complete set of EMV4.1 / ISO7816 libraries
• Turnkey PC/SC firmware and host drivers
o Multiple OS supported
Rev. 1.4
© 2009 Teridian Semiconductor Corporation
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DS_1210F_001
73S1210wFwDwa.DtaataSShheeete4Ut .com
Tables
Table 1: 73S1210 Pinout Description ........................................................................................................... 8
Table 2: MPU Data Memory Map ............................................................................................................... 11
Table 3: Flash Special Function Registers ................................................................................................. 13
Table 4: Internal Data Memory Map ........................................................................................................... 14
Table 5: Program Security Registers .......................................................................................................... 17
Table 6: IRAM Special Function Registers Locations ................................................................................ 18
Table 7: IRAM Special Function Registers Reset Values .......................................................................... 19
Table 8: XRAM Special Function Registers Reset Values ......................................................................... 20
Table 9: PSW Register................................................................................................................................ 21
Table 10: Port Registers ............................................................................................................................. 21
Table 11: Frequencies and Mcount Values for MCLK = 96MHz ................................................................ 23
Table 12: The MCLKCtl Register ................................................................................................................ 23
Table 13: The TCON Register .................................................................................................................... 24
Table 14: The INT5Ctl Register .................................................................................................................. 30
Table 15: The MISCtl0 Register.................................................................................................................. 30
Table 16: The MISCtl1 Register.................................................................................................................. 31
Table 17: The MCLKCtl Register ................................................................................................................ 31
Table 18: The PCON Register .................................................................................................................... 32
Table 19: The IEN0 Register ...................................................................................................................... 34
Table 20: The IEN1 Register ...................................................................................................................... 35
Table 21: The IEN2 Register ...................................................................................................................... 35
Table 22: The TCON Register .................................................................................................................... 36
Table 23: The T2CON Register .................................................................................................................. 36
Table 24: The IRCON Register................................................................................................................... 37
Table 25: External MPU Interrupts.............................................................................................................. 37
Table 26: Control Bits for External Interrupts.............................................................................................. 38
Table 27: Priority Level Groups .................................................................................................................. 38
Table 28: The IP0 Register ......................................................................................................................... 38
Table 29: The IP1 Register ......................................................................................................................... 39
Table 30: Priority Levels.............................................................................................................................. 39
Table 31: Interrupt Polling Sequence.......................................................................................................... 39
Table 32: Interrupt Vectors ......................................................................................................................... 39
Table 33: UART Modes .............................................................................................................................. 40
Table 34: Baud Rate Generation ................................................................................................................ 40
Table 35: The PCON Register .................................................................................................................... 41
Table 36: The BRCON Register ................................................................................................................. 41
Table 37: The MISCtl0 Register.................................................................................................................. 42
Table 38: The S0CON Register .................................................................................................................. 43
Table 39: The S1CON Register .................................................................................................................. 44
Table 40: The TMOD Register.................................................................................................................... 45
Table 41: Timers/Counters Mode Description ............................................................................................ 45
Table 42: The TCON Register .................................................................................................................... 46
Table 43: The IEN0 Register ...................................................................................................................... 47
Table 44: The IEN1 Register ...................................................................................................................... 48
Table 45: The IP0 Register ......................................................................................................................... 48
Table 46: The WDTREL Register ............................................................................................................... 48
Table 47: Direction Registers and Internal Resources for DIO Pin Groups ............................................... 49
Table 48: UDIR Control Bit ......................................................................................................................... 49
Table 49: Selectable Controls Using the UxIS Bits..................................................................................... 49
Table 50: The USRIntCtl1 Register ............................................................................................................ 50
Table 51: The USRIntCtl2 Register ............................................................................................................ 50
Table 52: The USRIntCtl3 Register ............................................................................................................ 50
Table 53: The USRIntCtl4 Register ............................................................................................................ 50
Table 54: The ACOMP Register ................................................................................................................. 51
Table 55: The INT6Ctl Register .................................................................................................................. 52
Table 56: The LEDCtl Register ................................................................................................................... 53
Rev. 1.4
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DS_1210F_001
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1.2 Hardware Overview
The 73S1210F single smart card controller integrates all primary functional blocks required to implement
a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up
to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface,
expansion smart card interface, serial interface, I2C interface, 6 x 5 keypad interface, RAM, FLASH
memory, and a variety of I/O pins.
The power management circuitry provides a 3.3V voltage output (VDD, pin #68) that must be connected
to the power supply inputs of the digital core of the circuit, pins # 28 and 40 (these are not internally
connected). Should external circuitry require a 3.3V digital power supply, the VDD output is capable of
supplying additional current.
Figure 1 shows a functional block diagram of the 73S1210F.
1.3 80515 MPU Core
1.3.1 80515 Overview
The 73S1210F includes an 80515 MPU (8-bit, 8051-compatible) that performs most instructions in one
clock cycle. The 80515 architecture eliminates redundant bus states and implements parallel execution
of fetch and execution phases. Normally a machine cycle is aligned with a memory fetch, therefore, most
of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (average)
improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.
Actual processor clocking speed can be adjusted to the total processing demand of the application
(cryptographic calculations, key management, memory management, and I/O management) using the
XRAM special function register MPUCKCtl.
Typical smart card, serial, keyboard and I2C management functions are available for the MPU as part of
the Teridian standard library. A standard ANSI “C” 80515-application programming interface library is
available to help reduce design cycle. Refer to the 73S12xxF Software User’s Guide.
1.3.2 Memory Organization
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three
memory areas: Program memory (Flash), external data memory (XRAM), and internal data memory
(IRAM). Data bus address space is allocated to on-chip memory as shown Table 2
Table 2: MPU Data Memory Map
Address
(hex)
0000-7FFF
0000-07FF
FC00-FFFF
Memory
Technology
Flash Memory
Static RAM
External SFR
Memory Type
Typical Usage
Non-volatile
Volatile
Volatile
Program and non-volatile data
MPU data XRAM
Peripheral control
Memory Size
(bytes)
32KB
2KB
1KB
Note: The IRAM is part of the core and is addressed differently.
Program Memory: The 80515 can address up to 32KB of program memory space from 0x0000 to
0xFFFF. Program memory is read when the MPU fetches instructions or performs a MOVC operation.
After reset, the MPU starts program execution from location 0x0000. The lower part of the program
memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte intervals, starting
from 0x0003. Reset is located at 0x0000.
Flash Memory: The program memory consists of flash memory. The flash memory is intended to
primarily contain MPU program code. Flash erasure is initiated by writing a specific data pattern to
Rev. 1.4
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