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PDF 73S8024RN Data sheet ( Hoja de datos )
| Número de pieza | 73S8024RN | |
| Descripción | Low Cost Smart Card Interface | |
| Fabricantes | Teridian Semiconductor | |
| Logotipo |  |
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73S8024RN
Low Cost Smart Card Interface
DATA SHEET
May 2010
DESCRIPTION
The Teridian 73S8024RN is a single smart card (ICC)
interface IC that can be controlled by a dedicated control
bus. The 73S8024RN has been designed to provide full
electrical compliance with ISO-7816-3, EMV 4.0
(EMV2000) and NDS specifications.
Interfacing with the system controller is done through a
control bus, composed of digital inputs to control the
interface, and one interrupt output to inform the system
controller of the card presence and faults.
The card clock can be generated by an on-chip oscillator
using an external crystal or by connection to a clock
signal.
The 73S8024RN incorporates an ISO-7816-3
activation/deactivation sequencer that controls the card
signals. Level-shifters drive the card signals with the
selected card voltage (3V or 5V), coming from an internal
Low Drop-Out (LDO) voltage regulator. This LDO
regulator is powered by a dedicated power supply input
VPC. Digital circuitry is separately powered by a digital
power supply VDD.
With its embedded LDO regulator, the 73S8024RN is a
cost effective solution for any application where a 5V
(typically -5% +10%) power supply is available.
Hardware support for auxiliary I/O lines, C4 / C8 contacts,
is provided*.
Emergency card deactivation is initiated upon card
extraction or upon any fault generated by the protection
circuitry. The fault can be a card over-current, a VDD
(digital power supply)**, a VPC (regulator power supply), a
VCC (card power supply) or an over-heating fault.
The card over-current circuitry is a true current detection
function, as opposed to VCC voltage drop detection, as
usually implemented in ICC interface ICs.
The VDD voltage fault has a threshold voltage that can be
adjusted with an external resistor or resistor network. It
allows automated card deactivation at a customized VDD
voltage threshold value. It can be used, for instance, to
match the system controller operating voltage range.
APPLICATIONS
• Set-Top-Box Conditional Access and Pay-per-
View
• Point of Sales and Transaction Terminals
• Control Access and Identification
* Pins/functions not available on 20-pin QFN package.
** User VDD_FLT threshold configuration not available on
20-pin QFN package.
ADVANTAGES
• Traditional step-up converter is replaced by a LDO
regulator:
Greatly reduced power dissipation
Fewer external components are required
Better noise performance
High current capability (90mA supplied to the card)
• SO28 package is pin-to-pin compatible with
industry-standard TDA8004 and TDA8024
• Card clock STOP (high and low) mode
• Small format (4x4x0.85mm) 20QFN package option
• True card over-current detection
FEATURES
• Card Interface:
Complies with ISO-7816-3, EMV 4.0 and NDS
A LDO voltage regulator provides 3V / 5V to the card
from an external power supply input
Provides at least 90mA to the card
ISO-7816-3 Activation / Deactivation sequencer with
emergency automated deactivation on card removal
or fault detected by the protection circuitry
Protection includes 3 voltage supervisors that detect
voltage drops on VCC (card), VDD (digital)**, and VPC
(regulator) power supplies
The VDD voltage supervisor threshold value can be
externally adjusted**
Over-current detection 150mA max
Card clock stop high or low*
2 card detection inputs, 1 for each possible user
polarity
Auxiliary I/O lines, for C4 / C8 contact signals*
Card CLK clock frequency up to 20MHz
• System Controller Interface:
3 Digital inputs control the card activation /
deactivation, card reset and card voltage
4 Digital inputs control the card clock (division rate
and card clock stop modes)
1 Digital output, interrupt to the system controller,
allows the system controller to monitor the card
presence and faults.
Crystal oscillator or host clock, up to 27MHz
• Regulator Power Supply:
4.75V to 5.5V (EMV 4.0)
4.85V to 5.5V (NDS)
• Digital Interfacing: 2.7V to 5.5V
• 6kV ESD Protection on the card interface
• Package: SO28, 20QFN or 32QFN
Rev. 1.9
© 2009 Teridian Semiconductor Corporation
1
1 page  
DS_8024RN_020
www.DataSheet4U.com
73S8024RN Data Sheet
1 Pin Description
CARD INTERFACE
Name
Pin
28SO
I/O 11
AUX1
13
AUX2
12
RST
CLK
16
15
PRES
PRES
VCC
GND
10
9
17
14
Pin
20QFN
5
–
–
8
7
4
3
9
6
Pin
32QFN
8
11
10
14
13
7
6
15
12
Description
Card I/O: Data signal to/from card. Includes a pull-up
resistor to VCC.
AUX1: Auxiliary data signal to/from card. Includes a
pull-up resistor to VCC.
AUX2: Auxiliary data signal to/from card. Includes a
pull-up resistor to VCC.
Card reset: provides reset (RST) signal to card.
Card clock: provides clock signal (CLK) to card. The rate
of this clock is determined by the external crystal
frequency or frequency of the external clock signal applied
on XTALIN and CLKDIV selections.
Card Presence switch: active high indicates card is
present. Should be tied to GND when not used, but it
Includes a high-impedance pull-down current source.
Card Presence switch: active low indicates card is
present. Should be tied to VDD when not used, but it
Includes a high-impedance pull-up current source.
Card power supply – logically controlled by sequencer,
output of LDO regulator. Requires an external filter
capacitor to the card GND.
Card ground.
MISCELLANEOUS INPUTS AND OUTPUTS
Name
Pin Pin Pin Description
28SO 20QFN 32QFN
XTALIN
24 15 23 Crystal oscillator input: can either be connected to crystal
or driven as a source for the card clock.
XTALOUT 25 16 24 Crystal oscillator output: connected to crystal. Left open
if XTALIN is being used as external clock input.
VDDF_ADJ
18
–
17 VDD fault threshold adjustment input: this pin can be used
to adjust the VDDF values (that controls deactivation of the
card). Must be left open if unused.
NC 5 – 2, 9, Non-connected pin.
16, 25,
32
POWER SUPPLY AND GROUND
Name
Pin Pin
28SO 20QFN
VDD
21 12
VPC
GND
GND
62
41
22 13
Pin
32QFN
20
3
1
21
Description
System interface supply voltage and supply voltage for
internal circuitry.
LDO regulator power supply source.
LDO Regulator ground.
Digital ground.
Rev. 1.9
5
5 Page 
DS_8024RN_020
www.DataSheet4U.com
73S8024RN Data Sheet
The following steps show the activation sequence and the timing of the card control signals when the
system controller pulls the CMDVCC low while the RSTIN is high:
• CMDVCC is set low.
• Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation,
the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to
the system controller, and the power VCC to the card is shut down.
• Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode.
• CLK is applied to the card at the end of (t3), after I/O is in reception mode.
• RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will
not set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
I/O
CLK
RSTIN
RST
t1
t2 t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5µs, I/O goes to reception state
t3 = > 0.5µs, CLK active
t4 ≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low
Rev. 1.9
11
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet 73S8024RN.PDF ] | |
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