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PDF AGL400 Data sheet ( Hoja de datos )
| Número de pieza | AGL400 | |
| Descripción | (AGLxxx) IGLOO Low-Power Flash FPGAs | |
| Fabricantes | Actel Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AGL400 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology
www.DataSheet4U.com
v1.3
®
Features and Benefits
Low Power
• 1.2 V to 1.5 V Core Voltage Support for Low Power
• Supports Single-Voltage System Operation
• 5 µW Power Consumption in Flash*Freeze Mode
• Low-Power Active FPGA Operation
• Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze
Mode
High Capacity
• 15 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal, Flash-Based CMOS Process
• Live-at-Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design When Powered Off
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except ARM®-enabled IGLOO®
devices) via JTAG (IEEE 1532–compliant)1
• FlashLock® to Secure FPGA Contents
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
IGLOO Product Family
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)
• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS
3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and
LVCMOS 2.5 V / 5.0 V Input1
• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-
LVDS (AGL250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold-Sparing I/Os‡
• Programmable Output Slew Rate1 and Drive Strength
• Weak Pull-Up/-Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages across the IGLOO Family
Clock Conditioning Circuit (CCC) and PLL1
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
•
•
1SRkAbMitsoafnFdlasFhIFROOsMwUithserVaNroianbvloe-laAtsipleecMt-eRmatoiory4,608-Bit1 RAM
•
Blocks (×1, ×2, ×4, ×9,
True Dual-Port SRAM
a(enxdce×p1t8×o1r8g)a1nizations)
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available
with or without Debug
IGLOO Devices
AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000
ARM-Enabled IGLOO Devices
M1AGL250 M1AGL400 M1AGL600 M1AGL1000
System Gates
15 k
30 k
60 k 125 k 250 k
400 k
600 k
1M
Typical Equivalent Macrocells
VersaTiles (D-flip-flops)
Flash*Freeze Mode (typical, µW)
RAM kbits (1,024 bits)
128
384
5
–
256 512 1,024 2,048 –
–
–
768
1,536 3,072
6,144
9,216
13,824
24,576
5
10 16
24
32
36
53
–
18 36
36
54 108
144
4,608-Bit Blocks
–
–
48
8
12 24
32
FlashROM Bits
Secure (AES) ISP 1
Integrated PLL in CCCs 2
VersaNet Globals 3
I/O Banks
Maximum User I/Os
1k
1k
1k 1k
1k
1k
1k
1k
–
–
Yes Yes
Yes
Yes
Yes
Yes
–
–
11
1
1
1
1
6
6
18 18
18
18
18
18
2
2
22
4
4
4
4
49
81
96 133 143 194 235
300
Package Pins
UC/CS
QFN
VQFP
FBGA
QN68
UC81/CS81
QN48, QN68,
QN132
VQ100
CS121
QN132
VQ100
FG144 5
CS196
QN132
VQ100
FG144
CS196 4
QN132 4,5
VQ100
FG144
CS196
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
CS281
FG144,
FG256,
FG484
Notes:
1. AES is not available for ARM-enabled IGLOO devices.
2. AGL060 in CS121 does not support the PLL.
3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.
4. The M1AGL250 device does not support this package.
5. Device/package support TBD
6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze
Technology handbook.
1 AGL015 and AGL030 devices do not support this feature.
‡ Supported only by AGL015 and AGL030 devices.
December 2008
© 2008 Actel Corporation
I
1 page  
1 – IGLOO Device Family Overview
www.DataSheet4U.com
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a
single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced
features.
The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low-
power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze
technology simplifies power management through I/O and clock management with rapid recovery
to operation mode.
The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW)
while the IGLOO device is completely functional in the system. This allows the IGLOO device to
control system power management based on external inputs (e.g., scanning for keyboard stimulus)
while consuming minimal power.
Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power,
single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-
market benefits at an ASIC-level unit cost.
These features enable designers to create high-density systems using existing ASIC or FPGA design
flows and tools.
IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as
clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and
AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates,
supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os.
M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM
for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA
fabric. It has a three-stage pipeline that offers a good balance between low-power consumption
and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction
set, has a configurable nested interrupt controller, and can be implemented with or without the
debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs.
The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support
AES decryption.
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit
ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off
I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze
technology is combined with in-system programmability, which enables users to quickly and easily
upgrade and update their designs in the final stages of manufacturing or in the field. The ability of
IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction
in power consumption, thus achieving the lowest total system power.
When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks
and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and
data is retained.
The availability of low-power modes, combined with reprogrammability, a single-chip and single-
voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices
the best fit for portable electronics.
v1.3
1-1
5 Page 
IGLOO Low-PowewrwFwla.DsahtaFSPheGetA4Us .com
All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay
operations as well as clock spine access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
• Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
• Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
• 2 programmable delay types for clock skew minimization
• Clock frequency synthesis (for PLL only)
Additional CCC specifications:
• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration (for PLL only).
• Output duty cycle = 50% ± 1.5% or better (for PLL only)
• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used (for PLL only)
• Maximum acquisition time is 300 µs (for PLL only)
• Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL
only)
• Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC (for PLL only)
Global Clocking
IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-ended
and differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these
banks determines the I/O standards supported.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
• Single-Data-Rate applications
• Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS
and M-LVDS can support up to 20 loads.
v1.3
1-7
11 Page | ||
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| PDF Descargar | [ Datasheet AGL400.PDF ] | |
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