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PDF LV8042LG Data sheet ( Hoja de datos )

Número de pieza LV8042LG
Descripción Bi-CMOS IC For Digital Still Cameras 7-Channel Single-Chip Motor Driver ICs
Fabricantes Sanyo Semiconductors 
Logotipo Sanyo Semiconductors Logotipo



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No Preview Available ! LV8042LG Hoja de datos, Descripción, Manual

Ordering number : ENA0004A
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LV8042LG Bi-CMOS IC
For Digital Still Cameras
7-Channel Single-Chip Motor Driver ICs
Overview
The LV8042LG is Motor driver 7ch single-chip for DSC.
Features
Micro-step driven stepping motor driver×2
PWM driven forward/reverse motor driver
(changeover to the micro-step driving stepping motor driver 1ch possible) × 2
PWM driven forward/reverse motor driver×2
Constant-current forward/reverse motor driver × 1
Two-phase, single-two phase full torque, single-two phase, 4W1-2, phase excitation drive changeover possible
(1/2/3/4ch)
Progress of micro-step driven excitation steps by clock signal input only (1/2/3/4ch)
Holding electrification current changeover in four steps possible by serial data (1/2/3/4ch)
Constant-current control chopping frequency variable with external resistor (1/2/3/4ch)
8-bit wire serial data control
Actuator application example
Shutter
Application 1
Constant current /VCM
Application 2
Constant current /VCM
Application 3
Constant current /VCM
Iris
Saturation /STM or VCM
Saturation /STM or VCM
Micro-step /STM
Focus
Micro-step /STM
Micro-step /STM
Micro-step /STM
Zoom
Micro-step /STM
Saturation /STM or DCM
Saturation /STM or DCM
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
41107 TI IM B8-8935,8943 No.A0004-1/29

1 page




LV8042LG pdf
Continued from preceding page.
Parameter
FC7 rapid charge current
FC7 steady charge current
FC7 steady discharge current
Current setting reference voltage
Serial data transmission pin
Logic pin input current
Logic input “H” level voltage
Logic input “L” level voltage
Minimum SCLK “H” pulse width
Minimum SCLK “L” pulse width
STB specified time
Minimum STB pulse width
Data setup time
Data hold time
Maximum SCLK frequency
LV8042LG
Symbol
Irafc7
Ichfc7
Idisfc7
VSEN41
VSEN42
VSEN43
VSEN44
(D7, D6)=(0, 0)
(D7, D6)=(0, 1)
(D7, D6)=(1, 0)
(D7, D6)=(1, 1)
Conditions
IINL5
IINH5
VINH5
VINL5
Tsch
Tscl
Tlat
Tlatw
Tds
Tdh
Fclk
VIN=0V (SCLK, DATA, STB)
VIN=3.3V (SCLK, DATA, STB)
SCLK, DATA, STB
SCLK, DATA, STB
SCLK
DATA
Fclk
Tsch Tscl
Tds Tdh
D0 D1
D2
STB
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min
300
5
5
0.190
0.124
0.090
0.056
Ratings
typ
450
10
10
0.200
0.134
0.100
0.066
max
600
15
15
0.210
0.144
0.110
0.076
Unit
µA
µA
µA
V
V
V
V
20
2.5
0.125
0.125
0.125
0.125
0.125
0.125
1.0 µA
33 50 µA
V
1.0 V
µs
µs
µs
µs
µs
µs
4 MHz
D6 D7
Tlat
Tlatw
No.A0004-5/29

5 Page





LV8042LG arduino
LV8042LG
5ch 6ch (PWM) Setting/7ch (constant-current) Reference Voltage Setting
Register No.
D0
D1
D2
D3
D4
D5
D6
D7
Data
1
1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Nomenclature
RG_SELECT 1
RG_SELECT 2
F/R5
DECAY5
F/R6
DECAY6
VSEN7_SELECT 1
VSEN7_SELECT 1
Functions
Register select 1
Register select 1
Forward/reverse setting
Current attenuation mode setting
Forward/reverse setting
Current attenuation mode setting
7ch constant-current reference voltage select 1
7ch constant-current reference voltage select 2
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Channel
5ch
PWM
6ch
PWM
7ch
Constant current
Serial Data Input Setting
ST
DATA
SCLK
D0 D1 D2 D3 D4 D5 D6 D7
STB
Status setting data latched
Input DATA and SCLK after setting of STB = “L”. SCLK is not accepted in the state with STB = “H”.
Input DATA from D0 to D7 in this order. CLK performs data transmission at the rise edge and latches all data at rise
of STB after transmission of all data.
All of serial data is reset to “0” with ST = “L”. and at the voltage to cut VCC low voltage.
Timing to Reflect Serial Data to the Output
PWM mode (Applicable to 3, 4, 5, and 6ch)
Type 1: FR and DECAY settings during PWM drive are reflected simultaneously with the STB signal of data
latching.
STP mode (Applicable to 1, 2, 3, and 4ch)
Type 1: HOLD, RESET, CUT ENABLE settings and reference voltage setting are reflected simultaneously with the
STB signal of data latching.
Type 2: Forward/reverse (F/R) and excitation mode (MS) settings made during STEP setting are reflected at rise of the
next clock of data latching.
CLK
STB
Data latch timing
Type 1
STB timing
CLK
STB
Type 2
Data latch timing
Reflect at rise
Example: Two-phase excitation Example: phases excitation
No.A0004-11/29

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