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PDF MAC7200 Data sheet ( Hoja de datos )
| Número de pieza | MAC7200 | |
| Descripción | MAC7200 Microcontroller Family Reference Manual | |
| Fabricantes | Freescale Semiconductor | |
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MAC7200RM
Rev. 2
04/2007
MAC7200 Microcontroller Family
Reference Manual
Devices Supported:
PAC7202 PAC7212
MAC7242
PAC7201 PAC7211
MAC7241
This document covers the following mask sets:
MAC72x2 – 0M34A, 1M34A, 0M84D, 1M84D
MAC72x1 – 0M19G
Freescale Semiconductor
MAC7200 Microcontroller Family Reference Manual, Rev. 2
i
1 page  
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
4.3.21
4.3.22
4.3.23
4.3.24
4.3.25
4.3.26
4.3.27
4.3.28
4.3.29
4.3.30
4.3.31
4.3.32
4.3.33
4.3.34
www.DataSheet4U.com
Signal Properties Summary ..............................................................................................33
Detailed Signal Descriptions .............................................................................................39
EXTAL, XTAL — Oscillator Pins.................................................................................39
RESET — External Reset Pin .......................................................................................39
XFC — PLL Loop Filter Pin .........................................................................................39
TDI — Test Data In Pin.................................................................................................40
TDO — Test Data Output Pin........................................................................................40
TCK — Test Clock Pin..................................................................................................40
TMS — Test Mode Pin..................................................................................................40
PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus ....................................40
PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and DSPI_B ............40
PA[9] / DATA[9] / PCS[3] / NEX1EVTI — Port A I/O Pin, External Databus,
DSPI_B and Nexus Primary ......................................................................................41
PA[10:15] / DATA[10:15] — Port A I/O Pins and external Databus ............................41
PB[0] / SDA / NEX1MCKO — Port B I/O Pin, IIC and Nexus Primary .....................41
PB[1] / SCL / NEX1EVTO — Port B I/O Pin, IIC and Nexus Primary .......................41
PB[2] / SIN_A / NEX1MSEO — Port B I/O Pin, DSPI_A and Nexus Primary...........41
PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus Primary .........42
PB[4] / SCK_A — Port B I/O Pin and DSPI_A............................................................42
PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A ................................................42
PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A ......................................................42
PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A ................................................42
PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..43
PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B ..............................................43
PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..........43
PB[12] / PCS[1] — Port B I/O Pin and DSPI_B...........................................................43
PB[13] / SCK_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary .........44
PB[14] / SOUT_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary.......44
PB[15] / SIN_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary...........44
PC[0:2] / ADDR[0:2] — Port C I/O Pins and External address bus .............................44
PC[3] / ADDR[3] / NEX2EVTI — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................44
PC[4] / ADDR[4] / NEX2MCKO — Port C I/O Pins, External Address Bus and
Nexus Secondary .......................................................................................................45
PC[5] / ADDR[5] / NEX2EVTO — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[6] / ADDR[6] / NEX2MSEO — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[7] / ADDR[7] / NEX2RDY — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External Address Bus and
Nexus Secondary .......................................................................................................46
PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control & Mode
Selection ....................................................................................................................46
Freescale Semiconductor
MAC7200 Microcontroller Family Reference Manual, Rev. 2
v
5 Page 
www.DataSheet4U.com
11.8.3
11.8.4
11.8.5
11.8.6
11.8.7
11.9
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.10
11.10.1
11.10.2
11.10.3
11.10.3.1
11.10.3.2
11.10.3.3
11.10.3.4
11.10.3.5
11.10.3.6
11.10.3.7
11.10.3.8
11.10.3.9
11.10.3.10
11.10.3.11
11.10.3.12
11.10.3.13
11.10.3.14
11.10.3.15
11.10.3.16
11.10.3.17
11.10.3.18
11.10.4
11.10.5
11.11
11.11.1
11.11.1.1
11.11.1.2
11.11.1.3
11.11.2
11.11.2.1
11.11.2.1.1
11.11.2.1.2
11.11.2.1.3
Resetting Nexus ...........................................................................................................141
Enabling Nexus............................................................................................................141
Disabling Nexus...........................................................................................................141
Nexus Development Status (DS) Register...................................................................142
Unintended Activation of Nexus .................................................................................142
External Signal Description .............................................................................................143
Functional Description.................................................................................................143
Pins Implemented ........................................................................................................143
Pin Protocol..................................................................................................................144
Rules for Output Messages ..........................................................................................146
Examples......................................................................................................................146
A7S Nexus3 Programmers Model ...................................................................................148
JTAG ID Register ........................................................................................................148
Nexus3 Register Map...................................................................................................150
A7S Nexus3 Register Definitions................................................................................151
Client Select Control (CSC) ....................................................................................151
Development Control (DC) .....................................................................................151
Development Status (DS) ........................................................................................152
User Base Address (UBA).......................................................................................153
Read/Write Access Control/Status (RWCS)............................................................154
Read/Write Access Data (RWD) .............................................................................155
Read/Write Access Address (RWA) ........................................................................156
Watchpoint Trigger (WT) ........................................................................................156
Data Trace Control (DTC).......................................................................................157
Data Trace Start Address (DTSA1, DTSA2)...........................................................158
Data Trace End Address (DTEA1, DTEA2) ...........................................................159
Breakpoint / Watchpoint Control (BWC1, BWC2) .................................................160
Breakpoint / Watchpoint Control (BWC3-6)...........................................................161
Breakpoint / Watchpoint Address (BWA1-6) ..........................................................161
Breakpoint / Watchpoint Address Mask (BWAM1, BWAM2)................................162
Breakpoint / Watchpoint Data (BWD1, BWD2) .....................................................162
Breakpoint / Watchpoint Data Mask (BWDM1, BWDM2) ....................................162
Port Configuration (PCR) ........................................................................................163
Nexus Register Access via JTAG ................................................................................164
Programming Considerations (RESET).......................................................................166
Functional Description.....................................................................................................166
Ownership Trace..........................................................................................................166
Ownership Trace Messaging (OTM).......................................................................166
OTM Error Messages ..............................................................................................166
OTM Flow ...............................................................................................................167
Program Trace..............................................................................................................167
Branch Trace Messaging (BTM) .............................................................................167
ARM7 Indirect Branch Message Instructions .....................................................168
ARM7 Direct Branch Message Instructions........................................................168
BTM in ARM mode ............................................................................................169
Freescale Semiconductor
MAC7200 Microcontroller Family Reference Manual, Rev. 2
xi
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAC7200.PDF ] | |
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