|
|
PDF CAT9552 Data sheet ( Hoja de datos )
| Número de pieza | CAT9552 | |
| Descripción | 16-Channel I2C-bus LED Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CAT9552 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
16-Channel I2C-bus LED Driver with
Programmable Blink Rate
www.DataSheet4U.com
CAT9552
FEATURES
16 LED drivers with On/Off and programmable
blink rate control
2 selectable, programmable blink rates:
– frequency: 0.172Hz to 44Hz
– duty cycle: 0% to 99.6%
16 open drain outputs drive 25mA each
I/Os can be used as GPIOs
400kHz I2C bus compatible
2.3V to 5.5V operation
5V tolerant I/Os
Active low reset input
RoHS-compliant 24-Lead SOIC, TSSOP and
24-pad TQFN (4 x 4mm) packages
APPLICATIONS
Office machines
Appliance control panels
Alarm systems
Point of sale displays
For Ordering Information details, see page 17.
DESCRIPTION
The CAT9552 is a 16-channel, parallel input/output
port expander optimized for LED On/Off and blinking
control. Each individual LED may be turned ON, OFF,
or set to blinking at one of two programmable rates.
The CAT9552 is compatible with I2C and SMBus
applications where it is desireable to limit the bus
traffic or free-up the bus master’s internal timer. Three
address pins allow up to eight CAT9552 devices to
occupy the same bus.
The CAT9552 contains an internal oscillator and two
PWM signals, which drive the LED outputs. The user
may program the period and duty cycle for each
individual PWM signal. After an initial set-up command
to program the Blink Rate 1 and Blink Rate 2 (frequency
and duty cycle), only one command from the bus master
is required to turn each individual open drain output ON,
OFF, or cycle at Blink Rate 1 or Blink Rate 2. Each open
drain LED output can sink a maximum current of 25mA.
The total continuous current sunk by all I/Os must not
exceed 200mA per package.
TYPICAL APPLICATION CIRCUIT
5V 5V
SDA
SCL
RESET
I2C/SMBus
Master
3 x 10kΩ
RS0 RS1
SDA VCC
SCL
RESET
LED0
LED1
CAT9552
LED11
A2 LED12
A1
A0
VSS LED15
RS11
GPIOs
Notes: LED0 to LED11 are shown being used as LED drivers
LED12 to LED15 are used as standard GPIOs
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No. MD-9005 Rev D
1 page  
www.DataCShAeeTt4U9.c5om52
A.C. CHARACTERISTICS
VCC = 2.3V to 5.5V, TA = -40ºC to +85ºC, unless otherwise specified(1)
Symbol Parameter
Standard I2C
Min Max
FSCL
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(2)
tF(2)
tSU:STO
tBUF(2)
tAA
tDH
Ti(2)
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
100
4
4.7
4
4.7
0
250
1000
300
4
4.7
3.5
100
100
Fast I2C
Min Max
400
0.6
1.3
0.6
0.6
0
100
300
300
0.6
1.3
0.9
50
100
Units
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
ns
ns
Symbol Parameter
Port Timing
tPV Output Data Valid
tPS Input Data Setup Time
tPH Input Data Hold Time
Reset
tW(2)
tREC
tRESET(3)
Reset Pulse Width
Reset Recovery Time
Time to Reset
Min Max Units
200
100
1
ns
ns
µs
10 ns
0 ns
400 ns
Notes:
(1) Test conditions according to "AC Test Conditions" table.
(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(3) The full delay to reset the part will be the sum of tRESET and the RC time constant of the SDA line.
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-9005 Rev D
5 Page 
www.DataCShAeeTt4U9.c5om52
External Reset Operation
The CAT9552 registers and the I2C state machine are
initialized to their default state when the RESET input
is held low for a minimum of tW. CAT9552’s registers
will be held in their default state until RESET returns
to a logic HIGH state. The external Reset timing is
shown in Figure 9.
Power-On Reset Operation
The CAT9552 incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state. The device is in a
reset state for VCC less than the internal POR
threshold level (VPOR). When VCC exceeds the VPOR
level, the reset state is released and the CAT9552
internal state machine and registers are initialized to
their default state. Thereafter VCC must be taken
below 0.2V to reset the device.
Slave Address
Data From Port
Data From Port
SDA
S 1 1 0 0 A2 A1 A0
A
DATA 1
A
DATA 4
NA P
READ FROM
PORT
Start Condition
R/W Acknowledge
From Slave
Acknowledge
From Master
No Acknowledge Stop
From Master Condition
DATA INTO
PORT
DATA 1
DATA 2
DATA 3
tph tps
DATA 4
Figure 8. Read Input Port Register Timing Diagram
SCL
START
SDA
30%
RESET
50%
tREC
LEDx
ACK OR READ CYCLE
50%
tRESET
50%
tW
tRESET
50% LED OFF
Figure 9. ¯R¯E¯S¯E¯T¯ Timing Diagram
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
11
Doc. No. MD-9005 Rev D
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CAT9552.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CAT9552 | 16-Channel I2C-bus LED Driver | ON Semiconductor |
| CAT9554 | 8-Bit I2C and SMBus I/O Port |  Catalyst Semiconductor |
| CAT9554A | 8-Bit I2C and SMBus I/O Port | Catalyst Semiconductor |
| CAT9555 | 16-Bit I2C and SMBus I/O Port | Catalyst Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |