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PDF CAT9534 Data sheet ( Hoja de datos )
| Número de pieza | CAT9534 | |
| Descripción | 8-bit I2C and SMBus I/O Port | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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8-bit I²C and SMBus I/O Port with Interrupt
www.DataSheet4U.com
CAT9534
FEATURES
400kHz I²C bus compatible
2.3V to 5.5V operation
Low stand-by current
5V tolerant I/Os
8 I/O pins that default to inputs at power-up
High drive capability
Individual I/O configuration
Polarity inversion register
Active low interrupt output
Internal power-on reset
No glitch on power-up
Noise filter on SDA/SCL inputs
Cascadable up to 8 devices
Industrial temperature range
RoHS-compliant 16-lead SOIC and TSSOP, and
16-pad TQFN (4 x 4mm) packages
APPLICATIONS
White goods (dishwashers, washing machines)
Handheld devices (cell phones, PDAs, digital
cameras)
Data Communications (routers, hubs and
servers)
BLOCK DIAGRAM (1)
DESCRIPTION
The CAT9534 is an 8-bit parallel input/output port
expander for I²C and SMBus compatible applications.
These I/O expanders provide a simple solution in
applications where additional I/Os are needed: sensors,
power switches, LEDs, pushbuttons, and fans.
The CAT9534 consists of an input port register, an
output port register, a configuration register, a polarity
inversion register and an I²C/SMBus-compatible serial
interface.
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The
system master can invert the CAT9534 input data by
writing to the active-high polarity inversion register.
The CAT9534 features an active low interrupt output
which indicates to the system master that an input
state has changed.
The device’s extended addressing capability allows up
to 8 devices to share the same bus.
CAT9534 is offered in 16 pin SOIC, TSSOP and
TQFN packages and operates over the full -40ºC to
+85ºC industrial temperature range.
For Ordering Information details, see page 15.
A0
A1
A2
SCL
SDA
VCC
VSS
INPUT
FILTER
POWER-ON
RESET
I2C/SMBUS
CONTROL
8-BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
LP FILTER
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6 VCC
I/O7
INT
Notes:
(1) All I/Os are set to inputs at RESET.
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
1
Doc. No. MD-9004 Rev. D
1 page  
A.C. TEST CONDITIONS
Input Rise and Fall time
CMOS Input Voltages
CMOS Input Reference Voltages
TTL Input Voltages
TTL Input Reference Voltages
Output Reference Voltages
Output Load: SDA, ¯IN¯T¯
Output Load: I/Os
www.DataShCeeAt4TU.9co5m34
≤ 10ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.4V to 2.4V
0.8V, 2.0V
0.5VCC
Current Source IOL = 3mA; CL = 100pF
Current Source: IOL/IOH = 10mA; CL = 50pF
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
Figure 1. I²C Serial Interface Timing
tSU:STO
tBUF
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
5
Doc. No. MD-9004 Rev. D
5 Page 
www.DataShCeeAt4TU.9co5m34
INTERRUPT OUTPUT
CAT9534’s interrupt otuput is an active LOW open-
drain output that is activated when any port pin
configured as an input changes state. The interrupt
output is reset when the input returns to its previous
state or the Input Port Register is read.
Note that changing an I/O from an output to an input
may cause a false interrupt to occur if the state of
the pin does not match the contents of the Input Port
register.
POWER-ON RESET OPERATION
When the power supply is applied to VCC pin, an
internal power-on reset pulse holds the CAT9534 in
a reset state until VCC reaches VPOR level. At this
point, the reset condition is released and the internal
state machine and the CAT9534’s registers are
initialized to their default state.
slave address
R/W
S 0 1 0 0 A2 A1 A0 0 A
acknowledge from slave
slave address
R/W
COMMAND BYTE
A S 0 1 0 0 A2 A1 A0 1 A
acknowledge from slave
acknowledge from slave
acknowledge
from master
data from register
DATA
first byte
A
At this moment master-transmitter becomes
master-receiver and slave-receiver
becomes slave-transmitter
no acknowledge
from master
data from register
DATA
last byte
NA P
Figure 10. Read from Register
SCL
123456 789
slave address
R/W
SDA S 0 1 0
start condition
0 A2 A1 A0 1
acknowledge
from slave
A
READ FROM
PORT
DATA INTO
PORT
DATA 1
tPH
data from port
DATA 1
acknowledge
from master
A
DATA 2
DATA 3
tPS
data from port
DATA 4
no acknowledge
from master
NA P
stop
condition
DATA 4
INT
tIV
tIR
Figure 11. Read Input Port Register
© 2010 SCILLC. All rights reserved
Characteristics subject to change without notice
11
Doc. No. MD-9004 Rev. D
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT9534.PDF ] | |
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