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PDF CAT5221 Data sheet ( Hoja de datos )
| Número de pieza | CAT5221 | |
| Descripción | Dual Digital Potentiometer | |
| Fabricantes | ON Semiconductor | |
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CAT5221
Dual Digital
Potentiometer (POT)
with 64 Taps
and I2C Interface
Description
The CAT5221 is two digital POTs integrated with control logic and
16 bytes of NVRAM memory. Each digital POT consists of a series of
63 resistive elements connected between two externally accessible end
points. The tap points between each resistive element are connected to
the wiper outputs with CMOS switches. A separate 6-bit control
register (WCR) independently controls the wiper tap switches for each
digital POT. Associated with each wiper control register are four 6-bit
non-volatile memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or any of the
non-volatile data registers is via a I2C serial bus. On power-up, the
contents of the first data register (DR0) for each of the four
potentiometers is automatically loaded into its respective wiper
control register (WCR).
The CAT5221 can be used as a potentiometer or as a two terminal,
variable resistor. It is intended for circuit level or system level
adjustments in a wide variety of applications.
Features
Two Linear-taper Digital Potentiometers
64 Resistor Taps per Potentiometer
End to End Resistance 2.5 kW, 10 kW, 50 kW or 100 kW
Potentiometer Control and Memory Access via I2C Interface
Low Wiper Resistance, Typically 80 W
Nonvolatile Memory Storage for Up to Four Wiper Settings for Each
Potentiometer
Automatic Recall of Saved Wiper Settings at Power Up
2.5 to 6.0 Volt Operation
Standby Current less than 1 mA
1,000,000 Nonvolatile WRITE Cycles
100 Year Nonvolatile Memory Data Retention
20-lead SOIC and TSSOP Packages
Industrial Temperature Range
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
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TSSOP−20
Y SUFFIX
CASE 948AQ
SOIC−20
W SUFFIX
CASE 751BJ
RW0
RL0
RH0
A0
A2
RW1
RL1
RH1
SDA
GND
PIN CONNECTIONS
1
CAT5221
SOIC−20 (W)
TSSOP−20 (Y)
(Top View)
VCC
NC
NC
NC
A1
A3
SCL
NC
NC
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 14
1
Publication Order Number:
CAT5221/D
1 page  
CAT5221
Table 5. D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Test Conditions
Min Typ Max
ICC
ISB
ILI
ILO
VIL
VIH
VOL1
Power Supply Current
Standby Current (VCC = 5.0 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = 3.0 V)
fSCL = 400 kHz
VIN = GND or VCC; SDA Open
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3 mA
−1
VCC x 0.7
1
1
10
10
VCC x 0.3
VCC + 1.0
0.4
Units
mA
mA
mA
mA
V
V
V
Table 6. CAPACITANCE (TA = 25C, f = 1.0 MHz, VCC = 5 V)
Symbol
Parameter
CI/O (Note 8)
CIN (Note 8)
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL)
Test Conditions
VI/O = 0 V
VIN = 0 V
Min Typ Max Units
8 pF
6 pF
Table 7. A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ Max Units
fSCL
TI (Note 8)
tAA
tBUF (Note 8)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR (Note 8)
tF (Note 8)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (For a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.2
0.6
1.2
0.6
0.6
0
100
0.6
50
400 kHz
50 ns
0.9 ms
ms
ms
ms
ms
ms
ns
ns
0.3 ms
300 ns
ms
ns
Table 8. POWER UP TIMING (Note 8) (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ Max Units
tPUR
Power-up to Read Operation
tPUW
Power-up to Write Operation
8. This parameter is tested initially and after a design or process change that affects the parameter.
1 ms
1 ms
Table 9. WRITE CYCLE LIMITS (Over recommended operating conditions unless otherwise stated.)
Symbol
Parameter
Min Typ Max Units
tWR Write Cycle Time
5 ms
NOTE: The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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5
5 Page 
INC/DEC
Command
Issued
SCL
SDA
CAT5221
tWRID
RW Voltage Out
Figure 13. Increment/Decrement Timing Limits
INSTRUCTION FORMAT
Table 13. READ WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
TC
A 0 1 0 1 A3 A2 A1 A0 K 1 0 0 1 0 P0 0
R
T
A DATA A S
C CT
0 K76543210KO
P
Table 14. WRITE WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
TC
A 0 1 0 1 A3 A2 A1 A0 K 1 0 1 0 0 P0 0
R
T
A DATA A S
C CT
0 K76543210KO
P
Table 15. READ DATA REGISTER (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
TC
C CT
A 0 1 0 1 A3 A2 A1 A0 K 1 0 1 1 0 P0 R1 R0 K 7 6 5 4 3 2 1 0 K O
RP
T
Table 16. WRITE DATA REGISTER (DR)
S DEVICE ADDRESSES A
INSTRUCTION
A
DATA
AS
TC
C CT
A 0 1 0 1 A3 A2 A1 A0 K 1 1 0 0 0 P0 R1 R0 K 7 6 5 4 3 2 1 0 K O
RP
T
Table 17. GLOBAL TRANSFER DATA REGISTER (DR) TO WIPER CONTROL REGISTER (WCR)
S DEVICE ADDRESSES A
INSTRUCTION
A
T CC
A 0 1 0 1 A3 A2 A1 A0 K 0 0 0 1 0 0 R1 R0 K
R
T
S
T
O
P
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