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PDF CDB4353 Data sheet ( Hoja de datos )
| Número de pieza | CDB4353 | |
| Descripción | 3.3 V Stereo Audio DAC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4353
3.3 V Stereo Audio DAC with 2 VRMS Line Output
Features
Multi-bit Delta-Sigma Modulator
106 dB A-wt Dynamic Range
-93 dB THD+N
Single-ended Ground Centered Analog
Architecture
– No DC-blocking Capacitors Required
– Integrated Step-up/Inverting Charge Pump
– Filtered Line-level Outputs
– Selectable 1 or 2 VRMS Full-scale Output
Low Clock-jitter Sensitivity
Low-latency Digital Filtering
Supports Sample Rates up to 192 kHz
24-bit Resolution
+3.3 V Charge Pump and Core Logic, +3.3 V
Analog, and +0.9 to 3.3 V Interface Power
Supplies
Low Power Consumption
24-pin QFN, Lead-free Assembly
Description
The CS4353 is a complete stereo digital-to-analog sys-
tem including digital interpolation, fifth-order multi-bit
delta-sigma digital-to-analog conversion, digital de-em-
phasis, analog filtering, and on-chip 2 VRMS line-level
driver from a 3.3 V supply.
The advantages of this architecture include ideal differ-
ential linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temper-
ature, high tolerance to clock jitter, and a minimal set of
external components.
The CS4353 is available in a 24-pin QFN package in
both Automotive (-40°C to +105°C) and Commercial
(-40°C to +85°C) grades. The CDB4353 Customer
Demonstration Board is also available for device evalu-
ation and implementation suggestions. Please see
“Ordering Information” on page 26 for complete details.
These features are ideal for cost-sensitive, 2-channel
audio systems including video game consoles, DVD
players and recorders, A/V receivers, set-top boxes,
digital TVs, mini-component systems, and mixing
consoles.
Interface Supply (VL)
+0.9 V to +3.3 V
Digital Core Logic and
Charge Pump Supply (VCP)
+3.3 V
Analog Supply (VA)
+3.3 V
Reset
Hardware
Control
Serial
Audio
Input
Hardware
Control
PCM Serial
Audio Port
Auto Speed
Mode Detect
Power-On
Reset
Interpolation
Filters
Multibit
∆Σ Modulator
DAC
Step-Up
Inverting
+VA_H
-VA_H
Ground-Centered,
2 Vrms Line Level Outputs
Left Channel
Pseudo Diff. Input
Right Channel
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
DEC '08
DS803PP1
1 page  
CS4353www.DataSheet4U.com
VA
VBIAS
RESET
1_2VRMS
DEM
I²S/LJ
LRCK
SDIN
Thermal Pad
17 Low Voltage Analog Power (Input) - Positive power supply for the analog section.
18 Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC.
Reset (Input) - Optional connection for an external reset control. The device enters a powered-down
19 state when this pin is set low (GND) OR when the VCP supply falls below the Voff threshold (see
Table 1). This pin should be set high (VL) during normal operation.
20
1 or 2 VRMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND)
selects 1 VRMS, while setting it high (VL) selects 2 VRMS.
21
De-emphasis (Input) - Selects the standard 50 µs/15 µs digital de-emphasis filter response for 44.1 kHz
sample rates when enabled.
22
Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND)
selects I²S, while setting it high (VL) selects Left-Justified.
23
Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial
audio data line.
24 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
-
Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated
from all board connections.
DS803PP1
5
5 Page 
CS4353www.DataSheet4U.com
DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground.
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
Symbol Min Typ Max Units
1.2 V < VL ≤ 3.3 V
0.9 V ≤ VL ≤ 1.2 V
VIH
VIH
0.7xVL
0.9xVL
-
-
-V
-V
1.2 V < VL ≤ 3.3 V VIL - - 0.3xVL V
0.9 V ≤ VL ≤ 1.2 V VIL - - 0.1xVL V
Iin - - ±10 µA
- 8 - pF
INTERNAL POWER-ON RESET THRESHOLD VOLTAGES
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground.
Parameters
Internal Reset Asserted at Power-On
Internal Reset Released at Power-On
Internal Reset Asserted at Power-Off
Symbol
Von1
Von2
Voff
Min
-
-
-
Typ
1.00
2.14
2.00
Max Units
-V
-V
-V
Table 1. Power-On Reset Threshold Voltages
VCP
Von2
Von1
DGND
reset
(internal)
HI
LO
reset reset
No Power undefined active
DAC
Ready
Voff
reset
active
Figure 2. Power-On Reset Threshold Sequence
DS803PP1
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet CDB4353.PDF ] | |
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