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PDF ADP4000 Data sheet ( Hoja de datos )
| Número de pieza | ADP4000 | |
| Descripción | Programmable Multi-Phase Synchronous Buck Converter | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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ADP4000
Product Preview
Programmable Multi- Phase
Synchronous Buck
Converter with PMBus
The ADP4000 is an integrated power control IC with a PMBus
interface. The ADP4000 can be programmed for 1-, 2-, 3-, 4-, 5- or 6-
phase operation, allowing for the construction of up to six
complementary buck switching stages. The ADP4000 supports PSI,
which is a power state indicator and can be used to reduce number of
operating phases at light loads. The ADP4000 includes a PMBus
interface, which can be used to program system set points such as
voltage offset, load line, phase balance and output voltage. Key system
performance data such as CPU current, CPU voltage, and power and
fault conditions can also be read back over the PMBus from the
ADP4000.
Features
• PMBus Interface
• Supports Both VR11 and VR11.1 Specifications
• Digitally Programmable 0.375 V to 1.6 V Output
• Additional 200 mV Offset Programmable (Max 1.8 V Output)
• Selectable 1-, 2-, 3-, 4-, 5-, or 6-Phase Operation
• Fast-Enhanced PWM FlexModet
• TRDET to Improve Load Release
• Active Current Balancing Between All Output Phases
• Supports On--The--Fly (OTF) VID Code Changes
• Supports PSI – Power Saving Mode
• This is a Pb--Free Device
Typical Applications
• Servers
• Desktop PC’s
• POLs (Memory)
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LFCSP40
CASE 932AD
MARKING
DIAGRAM
ADP4000
JCPZ
#YYWW
XXXXX
CCCCC
xx = Device Code
# = Pb--Free Package
YYWW = Date Code
XXX = Assembly Lot
CCC = Country of Origin
PIN ASSIGNMENT
ALERT 1
FAULT 2
SDA 3
SCL 4
EN 5
GND 6
ADD / VSENSE2 7
VSENSE1 8
IMON 9
TTSENSE 10
VRHOT 11
IREF 12
PIN 1
INDICATOR
ADP4000
TOP VIEW
(Not to Scale)
36 PWM1
35 PWM2
34 PWM3
33 PWM4
32 PWM5
31 PWM6
30 SW1
29 SW2
28 SW3
27 SW4
26 SW5
25 SW6
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2008
June, 2008 -- Rev. P0
1
ORDERING INFORMATION
Device*
Package
Shipping†
ADP4000JCPZ--REEL LFCSP48 2500/Tape & Reel
ADP4000JCPZ--RL7 LFCSP48 750/Tape & Reel
*The “Z’ suffix indicates Pb--Free package.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
ADP4000/D
1 page  
PIN ASSIGNMENT
Pin No. Pin Name
1 ALERT
2 FAULT
3 SDA
4 SCL
5 EN
6 GND
7 ADD/
VSENSE2
8 VSENSE1
9 IMON
10 TTSENSE
11 VRHOT
12 IREF
13 RT
14 RAMPADJ
15 TRDET
16 FBRTN
17 COMP
18 FB
19 CSREF
20 CSSUM
21 CSCOMP
22 ILIMFS
23 ODN
24 OD1
25 to 30
31 to 36
SW6 to
SW1
PWM6 to
PWM1
37
38 to 45
46
47
VCC
VID7 to
VID0
PSI
PWRGD
48 VCC3
ADP4000
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Description
ALERT Output. Open drain output that asserts low when the VR exceeds a programmable limit.
FAULT Output. Open drain output that asserts low when a fault has occurred. This fault can be due to VR or
current--limit, crowbar, or undervoltage. The trip points are loaded into registers.
Digital Input Output. PMBus serial data bi--directional pin. Requires PMBus pullup.
Digital Input. PMBus serial bus clock open drain input. Requires PMBus pullup.
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
PMBus Address Input. Connect a resistor to ground to select one of 8 addresses. This input is reconfigured
after startup as an analog voltage monitor, VSENSE2.
Analog Input. Measures an input voltage between 0 and 2.0 V and reports this back over the PMBus interface.
Total Current Output Pin.
VR Temperature Sense Input. An NTC thermistor between this pin and GND is used to remotely sense the
temperature at the desired thermal monitoring point.
VR HOT Output. Open drain output that signals when the temperature at the monitoring point connected to
TTSENSE exceeds the VRHOT temperature threshold.
Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB,
IILIMFS, and ITH(X).
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Transient Detect. This output is asserted low whenever a load release is detected
Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
Error Amplifier Output and Compensation Point.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between
this pin and the output voltage sets the no load offset point.
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier and the Power--Good and crowbar functions. This pin should be connected to the common point of
the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of
the current sense amplifier and the positioning loop response time.
Current Sense and Limit Scaling Pin. An external resistor from this pin to CSCOMP sets the internal current
sensing signal for current--limit and IMON. This value can be over--written using PMBus interface.
Output Disable Logic Output for PSI operation. This pin is actively pulled low when PSI is low, otherwise it
functions in the same way as OD1.
Output Disable Logic Output. This pin
UVLO threshold to signal to the Driver
iIsCatchtaivtetlhyepdurlilveedrlohwighw--hseidnethaendENlowin--psuidt eisolouwtpuotrswshheonulVdCgCo
is below
low.
its
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
Logic--Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3121. Connecting PWM6 to VCC disables PWM6, connecting PWM5 to VCC disables PWM5 and PWM6,
etc. This means the ADP4000 can be setup to operate as a 1-- 2--, 3--, 4--, 5--, or 6--phase controller.
Supply Voltage for the Device. A 340 Ω resistor should be placed between the 12 V system supply and the
VCC pin. The internal shunt regulator maintains VCC = 5.0 V.
Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open.
When in normal operation mode, the DAC output programs the FB regulation voltage from 0.375 V to 1.6 V.
Power State Indicator. Pulling this pin low places the controller in lower power state operation.
Power--Good Output. Open--drain output that signals when the output voltage is outside of the proper
operating range.
3.3 V Power Supply Output. A capacitor from this pin to ground provided decoupling for the interval 3.3 V LDO.
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5
5 Page 
ADP4000
Description
The ADP4000 is a 6--Phase VR11.1 regulator with a
PMBus Interface Typical application circuits is shown in
Figure 2.
Startup Sequence
The ADP4000 follows the VR11 start-up sequence shown
in Figure 7. After both the EN and UVLO conditions are
met, a programmable internal timer goes through one delay
cycle TD1. This delay cycle is programmed using Delay
Command, default delay = 2 ms, see Table 1 for
programmable values). The first six clock cycles of TD2 are
blanked from the PWM outputs and used for phase detection
as explained in the following section. Then the
programmable internal soft--start ramp is enabled (TD2) and
the output comes up to the boot voltage of 1.1V. The boot
hold time is also set by Delay Command. This second delay
cycle is called TD3. During TD3 the processor VID pins
settle to the required VID code. When TD3 is over, the
ADP4000 reads the VID inputs and soft--starts either up or
down to the final VID voltage (TD4). After TD4 has been
completed and the PWRGD masking time (equal to VID on
the fly masking) is finished, a third cycle of the internal timer
sets the PWRGD blanking (TD5).
The internal delay and soft--start times are programmable
using the serial interface and the Delay Command and the
Soft--Start Commands.
5.0 V
SUPPLY
UVLO
THRESHOLD
VTT I/O
(ADP4000 EN)
VCC_CORE
VR READY
(ADP4000 PWRGD)
CPU
VID INPUTS
0.85 V
TD1
TD3
V(1B.O1OVT)
TD2
VVID
TD4
VID INVALID
50 ms
TD5
VID VALID
Figure 7. System Startup Sequence for VR11
Internal Delay Timer
An internal timer sets the delay times for the startup
sequence, TD1, TD3 and TD5. The default time is 2msec,
which can be changed using the PMBus interface. This timer
is used for multiple delay timings (TD1, TD3 and TD5)
during the startup sequence. Also, it is used for timing the
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current--limit latchoff as explained in the Current--Limit
section. The current--limit timer is set to 4 times the delay
timer.
Table 1. Delay Codes
Code
Delay (msec)
000 0.5
001 1
010 1.5
011 2 = default
100 2.5
101 3
110 3.5
111 4
The delay timer is programmed using Bits <2:0> of the
Ton Delay command (0xD4). The delay can be programmed
between 0.5 msec and 4 msec. Table 1 provides the
programmable delay times.
Soft--Start
The soft--start slope for the output voltage is set by an
internal timer. The default value is 0.5 V/msec, which can be
programmed through the PMBus interface. After TD1 and
the phase detection cycle have been completed, the SS time
(TD2 in Figure 7) starts. The SS circuit uses the internal VID
DAC to increase the output voltage in 6.25 mV steps up to
the 1.1 V boot voltage.
Once the SS circuit has reached the boot voltage, the boot
voltage delay time (TD3) is started. The end of the boot
voltage delay time signals the beginning of the second
soft--start time (TD4). The SS voltage changes from the boot
voltage to the programmed VID DAC voltage (either higher
or lower) using 6.25 mV steps.
The soft--start slew rate is programmed using Bits <2:0>
of the Ton_Rise (0xD5) command code. Table 2 provides
the soft--start values
Table 2. Slew Rate Codes
Code
000
001
010
011
100
101
110
111
Slew Rate (V/msec)
0.1
0.3
0.5 = default
0.7
0.9
1.1
1.3
1.5
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP4000.PDF ] | |
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