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PDF NCP3218A Data sheet ( Hoja de datos )
| Número de pieza | NCP3218A | |
| Descripción | Mobile CPU Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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ADP3212A, NCP3218A
www.DataSheet4U.com
7-Bit, Programmable,
3-Phase, Mobile CPU
Synchronous Buck Controller
The APD3212A/NCP3218A is a highly efficient, multi−phase,
synchronous buck switching regulator controller. With its integrated
drivers, the APD3212A/NCP3218A is optimized for converting the
notebook battery voltage into the core supply voltage required by high
performance Intel processors. An internal 7−bit DAC is used to read a
VID code directly from the processor and to set the CPU core voltage
to a value within the range of 0.3 V to 1.5 V. The APD3212A/
NCP3218A is programmable for 1−, 2−, or 3−phase operation. The
output signals ensure interleaved 2− or 3−phase operation.
The APD3212A/NCP3218A uses a multimode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The
APD3212A/NCP3218A switches between single− and multi−phase
operation to maximize efficiency with all load conditions. The chip
includes a programmable load line slope function to adjust the output
voltage as a function of the load current so that the core voltage is
always optimally positioned for a load transient. The
APD3212A/NCP3218A also provides accurate and reliable
short−circuit protection, adjustable current limiting, and a delayed
power−good output. The IC supports On−The−Fly (OTF) output
voltage changes requested by the CPU.
The APD3212A/NCP3218A are specified over the extended
commercial temperature range of −40°C to 100°C. The ADP3212A is
available in a 48−lead QFN 7x7mm 0.5mm pitch package. The
NCP3218A is available in a 48−lead QFN 6x6mm 0.4mm pitch
package. Except for the packages, the APD3212A/NCP3218A are
identical. APD3212A/NCP3218A are Halogen−Free, Pb−Free and
RoHS compliant.
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1 48
QFN48
CASE 485AJ
1 48
QFN48
CASE 485AN
MARKING DIAGRAM
1
xxP321xA
AWLYYWWG
xxx = Specific Device Code
(ADP3212A or NCP3218A)
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
Features
• Single−Chip Solution
• Fully Compatible with the Intel® IMVP−6.5t
Specifications
• Selectable 1−, 2−, or 3−Phase Operation with Up to
1 MHz per Phase Switching Frequency
• Phase 1 and Phase 2 Integrated MOSFET Drivers
• Input Voltage Range of 3.3 V to 22 V
• Guaranteed ±8 mV Worst−Case Differentially Sensed
Core Voltage Error Over Temperature
• Automatic Power−Saving Mode Maximizes Efficiency
with Light Load During Deeper Sleep Operation
• Active Current Balancing Between Output Phases
• Independent Current Limit and Load Line Setting
Inputs for Additional Design Flexibility
• Built−In Power−Good Blanking Supports Voltage
Identification (VID) On−The−Fly (OTF) Transients
• 7−Bit, Digitally Programmable DAC with 0.3 V to
1.5 V Output
• Short−Circuit Protection with Programmable Latchoff
Delay
• Clock Enable Output Delays the CPU Clock Until the
Core
Voltage is Stable
• Output Power or Current Monitor Options
• 48−Lead QFN 7x7mm (ADP3212A), 48−Lead QFN
6x6mm (NCP3218A)
• These are Pb−Free Devices
• Fully RoHS Compliant
Applications
• Notebook Power Supplies for Next−Generation Intel
Processors
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 33 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 0
1
Publication Order Number:
ADP3212A/D
1 page  
ADP3212A, NCP3218A
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ELECTRICAL CHARACTERISTICS
VCC = PVCC = 5.0 V, FBRTN = PGND = GND = 0 V, H = 5.0 V, L = 0 V, EN = VARFREQ = H, DPRSLP = L, PSI = 1.05 V,
VVID = VDAC = 1.2000 V, TA = −40°C to 100°C, unless otherwise noted. (Note 1) Current entering a pin (sink current) has a positive sign.
Parameter
Symbol
Conditions
Min Typ Max Units
VOLTAGE CONTROL − VOLTAGE ERROR AMPLIFIER (VEAMP)
FB, LLINE Voltage Range (Note 2)
VFB, VLLINE
Relative to CSREF = VDAC
−200
+200
mV
FB, LLINE Offset Voltage (Note 2)
VOSVEA
Relative to CSREF = VDAC
−0.5 +0.5 mV
LLINE Bias Current
ILLINE
−100
+100
nA
FB Bias Current
IFB
−1.0 +1.0 mA
LLINE Positioning Accuracy
VFB − VVID Measured on FB relative to VVID, LLINE −77.5 −80 −82.5 mV
forced 80 mV below CSREF
COMP Voltage Range (Note 2)
COMP Current
VCOMP
ICOMP
COMP = 2.0 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
0.85
−0.75
6.0
4.0
V
mA
COMP Slew Rate
SRCOMP
CCOMP = 10 pF, CSREF = VDAC,
Open loop configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
V/ms
15
−20
Gain Bandwidth (Note 2)
VID DAC VOLTAGE REFERENCE
GBW
Non−inverting unit gain configuration,
RFB = 1 kW
20 MHz
VDAC Voltage Range (Note 2)
See VID table
0 1.5 V
VDAC Accuracy
VFB − VVID
Measured on FB (includes offset),
relative to VVID
VVID = 0.5000 V to 1.5000 V,
T = −10°C to 100°C
VTV=ID−=400°.C50t0o01V00t°oC1.5000 V,
VVID = 0.3000 V to 0.4875 V,
T = −10°C to 100°C
VVID = 0.3000 V to 0.4875 V,
T = −40°C to 100°C
−7.5
−9.0
−9.0
−10
mV
+7.5
+9.0
+9.0
+10
VDAC Differential Non−linearity
(Note 2)
−1.0 +1.0 LSB
VDAC Line Regulation
VDAC Boot Voltage
Soft−Start Delay (Note 2)
ΔVFB
VBOOTFB
tDSS
VCC = 4.75 V to 5.25 V
Measured during boot delay period
Measured from EN pos edge to
FB = 50 mV
0.001
1.100
200
%
V
ms
Soft−Start Time
tSS Measured from FB = 50 mV to FB settles
to 1.1 V within 5%
1.4
ms
Boot Delay
tBOOT
Measured from FB settling to 1.1 V within
5% to CLKEN neg edge
60
ms
VDAC Slew Rate (Note 2)
Soft−Start
Non−LSB VID step, DPRSLP = H, Slow
C4 Entry/Exit
Non−LSB VID step, DPRSLP = L, Fast
C4 Exit
LSB VID step, DVID transition
GPU Mode, Non−LSB VID step, Fast
Entry/Exit
0.0625
0.25
1.0
0.4
1.0
LSB/
ms
FBRTN Current
IFBRTN
VOLTAGE MONITORING and PROTECTION − POWER GOOD
−90 −200 mA
CSREF Undervoltage Threshold
CSREF Overvoltage Threshold
VUVCSREF
VOVCSREF
Relative to nominal VDAC voltage
Relative to nominal VDAC voltage,
T = −10°C to 100°C
T = −40°C to 100°C
−240
150
140
−300
200
200
1. All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2. Guaranteed by design or bench characterization, not production tested.
3. Based on bench characterization data.
4. Timing is referenced to the 90% and 10% points, unless otherwise noted.
−360
250
250
mV
mV
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5
5 Page 
ADP3212A, NCP3218A
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
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400
350
300 VARFREQ = 0 V
1000
VID = 1.4125 V
VID = 1.2125 V
250
VARFREQ = 5 V
200
VID = 1.1 V
150 VID = 0.8125 V
100
50
0
0.25
0.50
RT = 187 kW
2 Phase Mode
0.75 1.00 1.25 1.50
VID OUTPUT VOLTAGE (V)
Figure 6. Switching Frequency vs. VID Output
Voltage in PWM Mode
VID = 0.6125 V
100
10
100 1000
Rt RESISTANCE (kW)
Figure 7. Per Phase Switching Frequency vs.
RT Resistance
Output Voltage
Output Voltage
1
2
3
4
1: 0.5 V/div
2: 2 V/div
3: 5 V/div
4: 5 V/div
PWRGD
CLKEN
1 ms/div
EN
GPU Mode
Figure 8. Startup in GPU Mode
1
PWRGD
2
3
4
1: 0.5 V/div
2: 2 V/div
CLKEN
3: 5 V/div
4: 5 V/div
EN
4 ms/div
CPU Mode
Figure 9. Startup in CPU Mode
Output Voltage
1
PWRGD
2
EN
3
4 1: 0.5 V/div
2: 2 V/div
3: 2 V/div
4: 2 V/div
CLKEN
200 ms/div 1 A Load
Figure 10. Shutdown
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| Páginas | Total 35 Páginas | |
| PDF Descargar | [ Datasheet NCP3218A.PDF ] | |
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