PDF DS1643P Data sheet ( Hoja de datos )

Número de pieza	DS1643P
Descripción	Nonvolatile Timekeeping RAMs
Fabricantes	Maxim Integrated Products
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No Preview Available ! 19-5058; Rev 5/10 www.DataSheet4U.com DS1643/DS1643P Nonvolatile Timekeeping RAMs www.maxim-ic.com FEATURES  Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source  Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations.  Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power  Access Times of 85ns and 100ns  BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100  Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance  Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time  DS1643 Only (DIP Module) Standard JEDEC Byte-Wide 8K x 8 RAM Pinout  UL Recognized  DS1643P Only (PowerCap Module Board) Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-Fail Output Pin-for-Pin Compatible with Other Densities of DS164XP Timekeeping RAM PIN CONFIGURATIONS N.C. TOP VIEW A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 28 2 3 27 DS1643 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC WE CE2 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 Encapsulated DIP (700-mil Extended) N.C. N.C. N.C. PFO VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 DS1643P 4 5 6 7 8 9 10 11 12 13 14 15 X1 GND VBAT X2 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 PowerCap Module Board (Uses DS9034PCX PowerCap) N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ORDERING INFORMATION PART VOLTAGE RANGE (V) TEMP RANGE PIN-PACKAGE DS1643-85+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1643-100+ 5.0 0°C to +70°C 28 EDIP (0.740) DS1643P-85+ 5.0 0°C to +70°C 34-PowerCap* DS1643P-100+ 5.0 0°C to +70°C 34-PowerCap* *DS9034I-PCX+ and DS9034-PCX+ required (must be ordered separately). +Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices. TOP MARK DS1643+85 DS1643+100 DS1643P+85 DS1643P+100 1 of 17 1 page DwSw1w6.D4a3t/aDShSee1t64U4.3coPm CLOCK ACCURACY (DIP MODULE) The DS1643 is guaranteed to keep time accuracy to within 1 minute per month at 25C. CLOCK ACCURACY (POWERCAP MODULE) The DS1643P and DS9034PCX are each individually tested for accuracy. Once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35ppm) at 25C. Table 2. Register Map—Bank1 ADDRESS B7 B6 B5 DATA B4 B3 B2 B1 B0 FUNCTION RANGE 1FFF ———————— Year 00-99 1FFE X X X ————— Month 01-12 1FFD X X —————— Date 01-31 1FFC 1FFB 1FFA X Ft X X X — — — X X —————— X ——————— Day Hour Minutes 01-07 00-23 00-59 1FF9 1FF8 OSC — — — — — — — WR XXXXXX Seconds Control 00-59 A OSC = STOP BIT W = WRITE BIT R = READ BIT X = UNUSED FT = FREQUENCY TEST Note: All indicated “X” bits are not used but must be set to “0” for proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1643 is in the read mode whenever WE (write enable) is high and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA , the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. WRITING DATA TO RAM OR CLOCK The DS1643 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. 5 of 17 5 Page POWER-UP/DOWN AC CHARACTERISTICS (VCC = 5.0V 10%, TA = 0C to +70C.) PARAMETER SYMBOL MIN CE or WE at VIH, CE2 at VIL, Before Power-down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VBAT VCC Rise Time: VPF(MIN) to VPF(MAX) Power-Up Recover Time Expected Data Retention Time (Oscillator On) tPD 0 tF 300 tFB 10 tR 0 tREC tDR 10 TYP MAX 35 DwSw1w6.D4a3t/aDShSee1t64U4.3coPm UNITS NOTES s s s s ms years 5, 6 POWER-UP/POWER-DOWN TIMING CAPACITANCE (TA = +25C) PARAMETER Capacitance on All Pins Capacitance on All Output Pins SYMBOL CIN CO MIN TYP MAX 7 10 UNITS pF pF NOTES 11 of 17 11 Page

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