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PDF PCA9574 Data sheet ( Hoja de datos )
| Número de pieza | PCA9574 | |
| Descripción | level translating - low voltage GPIO | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 02 — 27 July 2009
Product data sheet
1. General description
The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere
between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the
8 I/O ports can be configured as an input or output independent of each other and default
on start-up to inputs. I/O expanders provide a simple solution when additional I/Os are
needed while keeping interconnections to a minimum; for example in battery powered
mobile applications and clamshell devices for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of
a processor running at one voltage level to I/O devices operating at a different (usually
higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices
extremely flexible in mixed signal environments where communication between
incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as
1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus hold with
programmable on-chip pull-up or pull-down feature for I/Os is also provided.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs on an input port unless that port is masked
(default = masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s
at the same time even if they have different individual I2C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal
Power-On Reset (POR) or hardware reset pin (RESET) initializes the 8 I/Os as inputs,
sets the registers to their default values and initializes the device state machine. The I/O
bank is held in its default state when the logic supply (VDD) is off.
One address select pin allows up to two PCA9574 devices to be connected with two
different addresses on the same I2C-bus.
1 page  
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
6. Pinning information
6.1 Pinning
terminal 1
index area
PCA9574BS
INT 1
A0 2
RESET 3
P0 4
P1 5
P2 6
P3 7
VSS 8
PCA9574PW
16 VDD
15 SDA
14 SCL
13 P7
12 P6
11 P5
10 P4
9 VDD(IO)
002aad052
Fig 3. Pin configuration for TSSOP16
RESET 1
P0 2
P1 3
P2 4
12 SCL
11 P7
10 P6
9 P5
002aad053
Transparent top view
Fig 4. Pin configuration for HVQFN16
terminal 1
index area
PCA9574HR
P0 1
P1 2
P2 3
P3 4
12 SDA
11 SCL
10 P7
9 P6
Transparent top view
Fig 5. Pin configuration for HXQFN16U
002aad876
PCA9574_2
Product data sheet
Rev. 02 — 27 July 2009
© NXP B.V. 2009. All rights reserved.
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NXP Semiconductors
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PCA9574
8-bit I2C-bus and SMBus, level translating, low voltage GPIO
7.5.6 Register 5 - Output port register
This register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 4. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value.
Table 10. Register 5 - Output port register (address 05h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 O0.7
R/W
0*
reflects outgoing logic levels of pins defined as
6 O0.6
R/W
0*
outputs by Register 4
5 O0.5
R/W
0*
4 O0.4
R/W
0*
3 O0.3
R/W
0*
2 O0.2
R/W
0*
1 O0.1
R/W
0*
0 O0.0
R/W
0*
7.5.7 Register 6 - Interrupt mask register
All the bits of Interrupt mask register are set to logic 1 upon power-on or software reset,
thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to
logic 0.
Table 11. Register 6 - Interrupt mask register (address 06h) bit description
Legend: * default value.
Bit Symbol Access Value Description
7 M0.7
R/W
1*
enable or disable interrupts
6 M0.6
R/W
1*
0 = enable interrupt
5 M0.5
R/W
1*
1 = disable interrupt (default value)
4 M0.4
R/W
1*
3 M0.3
R/W
1*
2 M0.2
R/W
1*
1 M0.1
R/W
1*
0 M0.0
R/W
1*
PCA9574_2
Product data sheet
Rev. 02 — 27 July 2009
© NXP B.V. 2009. All rights reserved.
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