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PDF ICS1894-32 Data sheet ( Hoja de datos )
| Número de pieza | ICS1894-32 | |
| Descripción | 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER | |
| Fabricantes | Integrated Device Technology | |
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DATASHEET
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
ICS1894-32
Description
The ICS1894-32 is a low-power, physical-layer device
(PHY) that supports the ISO/IEC 10Base-T and
100Base-TX Carrier-Sense Multiple Access/Collision
Detection (CSMA/CD) Ethernet standards, ISO/IEC
8802.3. It is intended for RMII/MII Node applications and
includes the Auto-MDIX feature that automatically corrects
crossover errors in plant wiring.
The ICS1894-32 incorporates Digital-Signal Processing
(DSP) control in its Physical-Medium Dependent (PMD)
sub-layer. As a result, it can transmit and receive data on
unshielded twisted-pair (UTP) category 5 cables with
attenuation in excess of 24 dB at 100MHz.
The ICS1894-32 provides a Serial-Management Interface
for exchanging command and status information with a
Station-Management (STA) entity. The ICS1894-32
Media-Dependent Interface (MDI) can be configured to
provide full-duplex operation at data rates of 10 Mb/s or
100Mb/s.
In addition, the ICS1894-32 includes a programmable LED
and interrupt output function. The LED outputs can be
configured through registers to indicate the occurance of
certain events such as LINK, COLLISION, ACTIVITY, etc.
The purpose of the programmable interrupt output is to
notify the PHY controller device immediately when a certain
event happens instead of having the PHY controller
continuously poll the PHY. The events that could be used to
generate interrupts are: receiver error, Jabber, page
received, parallel detect fault, link partner acknowledge, link
status change, auto-negotiation complete, remote fault,
collision, etc.
The ICS1894-32 has deep power modes that can result in
significant power savings when the link is broken.
Applications: NIC cards, PC motherboards, switches,
routers, DSL and cable modems, game machines, printers,
network connected appliances, and industrial equipment.
Features
• Supports category 5 cables and above with attenuation in
excess of 24dB at 100 MHz.
• Single-chip, fully integrated PHY provides PCS, PMA,
PMD, and AUTONEG sub layers functions of IEEE
standard.
• 10Base-T and 100Base-TX ISO/IEC 8802.3 compliant
• MIIM (MDC/MDIO) management bus for PHY register
configuration
• RMII interface support with external 50 MHz system clock
• Single 3.3V power supply
• Highly configurable, supports:
– Media Independent Interface (MII)
– Auto-Negotiation with Parallel detection
– Node applications, managed or unmanaged
– 10M or 100M full duplex modes
– Loopback mode for Diagnostic Functions
• Auto-MDI/MDIX crossover correction
• Low-power CMOS (typically 300 mW)
• Power-Down mode (typically 21mW)
• Clock and crystal supported in MII mode
• Programmable LEDs
• Interrupt output pin
• Fully integrated, DSP-based PMD includes:
– Adaptive equalization and baseline-wander
correction
– Transmit wave shaping and stream cipher
scrambler
– MLT-3 encoder and NRZ/NRZI encoder
• Core power supply (3.3 V)
• 3.3 V/1.8 V VDDIO operation supported
• Smart power control with deep power down feature
• Available in 32-pin (5mm x 5mm) QFN package, Pb-free
• Available in Industrial Temp and Lead Free
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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ICS1894-32 REV K 060110
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
www.DataSPhHeeYt4CUE.coIVmER
Strapping Options
Pin
Number
Pin
Name
14 AMDIX/RXD3
15 P3/RXD2
11 P2/INT
31 P0/LED0
32 P1/ISO/LED1
16 RXTRI/RXD1
17 FDPX/RXD0
18 RMII/RXDV
20 ANSEL/RXCLK
21 NOD/RXER
22 SPEED/TXCLK
Pin
Type1
IO/Ipu
IO/Ipd
IO/Ipd
IO
IO
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
IO/Ipd
IO/Ipu
Pin Function
1 = AMDIX enable
0 = AMDIX disable
The PHY address is set by P[3:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
1 = Real time receiver isolation function enable3; 0 = Receiver Tristate Disable
1=Full duplex
0=Half duplex (mode not supported)
Ignored if Auto negotiation is enabled
1 = RMII mode
0 = MII mode
1=Enable auto negotiation
0=Disable auto negotiation
0=Node mode
1=repeater mode (mode not supported)
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. IO/Ipd = Digital Input with internal 20k pull-down during power on reset/hardware reset; output pin otherwise.
3. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
Functional Description
The ICS1894-32 is an ethernet PHYceiver. During data
transmission, it accepts sequential nibbles/di-bits from the
MAC (Media Access Control), converts them into a serial bit
stream, encodes them, and transmits them over the medium
through an external isolation transformer. When receiving
data, the ICS1894-32 converts and decodes a serial bit
stream (acquired from an isolation transformer that
interfaces with the medium) into sequential nibbles/di-bits. It
subsequently presents these nibbles/di-bits to the MAC
Interface.
The ICS1894-32 implements the OSI model’s physical
layer, consisting of the following, as defined by the ISO/IEC
8802-3 standard:
• Physical Coding sublayer (PCS)
• Physical Medium Attachment sublayer (PMA)
• Physical Medium Dependent sublayer (PMD)
• Auto-Negotiation sublayer
The ICS1894-32 is transparent to the next layer of the OSI
model, the link layer. The link layer has two sublayers: the
Logical Link Control sublayer and the MAC sublayer. The
ICS1894-32 can interface directly with the MAC via MII/RMII
interface signals.
The ICS1894-32 transmits framed packets acquired from its
MAC Interface and receives encapsulated packets from
another PHY, which it translates and presents to its MAC
Interface.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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ICS1894-32
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
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are ignored by the MAC.
Receive Error (RX_ER)
RX_ER is asserted for one or more REFIN periods to
indicate that an error (e.g. a coding error or any error that a
PHY is capable of detecting, and that may otherwise be
undetectable by the MAC sub-layer) was detected
somewhere in the frame presently being transferred from
the PHY. RX_ER transitions synchronously with respect to
REFIN. While CRS_DV is de-asserted, RX_ER has no
effect on the MAC.
Auto-MDI/MDIX Crossover
The ICS1894-32 includes the auto-MDI/MDIX crossover
feature. In a typical CAT 5 Ethernet installation the transmit
twisted pair signal pins of the RJ45 connector are crossed
over in the CAT 5 wiring to the partners receive twisted pair
signal pins and receive twisted pair to the partners transmit
twisted pair. This is usually accomplished in the wiring plant.
Hubs generally wire the RJ45 connector crossed to
accomplish the crossover. Two types of CAT 5 cables
(straight and crossed) are available to achieve the correct
connection. The Auto-MDI/MDIX feature automatically
corrects for miss-wired installations by automatically
swapping transmit and receive signal pairs at the PHY when
no link results. Auto-MDI/MDIX is automatic, but may be
disabled for test purposes by writing MDIO register 19 Bits
9:8 in the MDIO register. The Auto-MDI/MDIX function is
independent of Auto-Negotiation and preceeds
Auto-Negotiation when enabled.
Auto MDI/MDIX Table
AMDIX_EN
(pin 14)
x
x
0
1
Default
1
AMDIX_EN
[Reg 19:9]
0
0
1
1
1
MDI_MODE
[Reg 19:8]
Tx/Rx MDI
Configuration
0 straight
1 cross
x straight
x straight/cross (auto
select)
0 straight/cross (auto
select)
Definitions:
straight transmit = TP_AP & TP_AN
receive = TP_BP & TP_BN
cross
transmit = TP_BP & TP_BN
receive = TP_AP & TP_AN
AMDIX_EN (Pin 14) AMDIX enable pin with 20 kOhm
pull-up resistor
AMDIX_EN [19:9] MDIO register 19h bit 9
MDI_MODE [19:8] MDIO register 19h bit 8
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
11
ICS1894-32 REV K 060110
11 Page | ||
| Páginas | Total 50 Páginas | |
| PDF Descargar | [ Datasheet ICS1894-32.PDF ] | |
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