PDF 25DF081 Data sheet ( Hoja de datos )

Número de pieza	25DF081
Descripción	AT25DF081
Fabricantes	ATMEL Corporation
Logotipo
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No Preview Available ! www.DataSheet4U.com Features • Single 1.65V - 1.95V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 66 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture – 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature – Sixteen 64-Kbyte Physical Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming – Byte/Page Program (1 to 256 Bytes) • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation – 7 mA Active Read Current (Typical) – 8 µA Deep Power-Down Current (Typical) • Endurance: 100,000 Program/Erase Cycles • Data Retention: 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (150-mil wide) – 8-contact Ultra Thin DFN (5 mm x 6 mm x 0.6 mm) – 11-ball dBGA (WLCSP) 8-megabit 1.65-volt Minimum SPI Serial Flash Memory AT25DF081 1. Description The AT25DF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF081, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF081 have been opti- mized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows addi- tional code routines and data storage segments to be added while still maintaining the same overall device density. 3674E–DFLASH–8/08 1 page Figure 4-1. Memory Architecture Diagram Block Erase Detail Internal Sectoring for Sector Protection Function 64KB (Sector 15) 64KB (Sector 14) 64KB Block Erase (D8h Command) 32KB Block Erase (52h Command) 4KB Block Erase (20h Command) Block Address Range 64KB 32KB 32KB 64KB 32KB 32KB 4KB 0F F F F F h – 0F F 000h 4KB 0F E F F F h– 0F E 000h 4KB 0F DF F F h – 0F D000h 4KB 0F CF F F h – 0F C000h 4KB 0F BF F F h – 0F B000h 4KB 0F AF F F h – 0F A000h 4KB 0F 9F F F h – 0F 9000h 4KB 0F 8F F F h – 0F 8000h 4KB 0F 7F F F h – 0F 7000h 4KB 0F 6F F F h – 0F 6000h 4KB 0F 5F F F h – 0F 5000h 4KB 0F 4F F F h – 0F 4000h 4KB 0F 3F F F h – 0F 3000h 4KB 0F 2F F F h – 0F 2000h 4KB 0F 1F F F h – 0F 1000h 4KB 0F 0F F F h – 0F 0000h 4KB 0E F F F F h– 0E F 000h 4KB 0E E F F F h– 0E E 000h 4KB 0E DF F F h – 0E D000h 4KB 0E CF F F h– 0E C000h 4KB 0E BF F F h– 0E B000h 4KB 0E AF F F h – 0E A000h 4KB 0E 9F F F h – 0E 9000h 4KB 0E 8F F F h – 0E 8000h 4KB 0E 7F F F h – 0E 7000h 4KB 0E 6F F F h – 0E 6000h 4KB 0E 5F F F h – 0E 5000h 4KB 0E 4F F F h – 0E 4000h 4KB 0E 3F F F h – 0E 3000h 4KB 0E 2F F F h – 0E 2000h 4KB 0E 1F F F h – 0E 1000h 4KB 0E 0F F F h – 0E 0000h 64KB (Sector 0) 64KB 32KB 32KB 4KB 00F F F F h – 00F 000h 4KB 00E F F F h – 00E 000h 4KB 00DF F F h – 00D000h 4KB 00CF F F h – 00C000h 4KB 00BF F F h – 00B000h 4KB 00AF F F h – 00A000h 4KB 009F F F h – 009000h 4KB 008F F F h – 008000h 4KB 007F F F h – 007000h 4KB 006F F F h – 006000h 4KB 005F F F h – 005000h 4KB 004F F F h – 004000h 4KB 003F F F h – 003000h 4KB 002F F F h – 002000h 4KB 001F F F h – 001000h 4KB 000F F F h – 000000h AT25DF081 www.DataSheet4U.com Page Program Detail 1-256 Byte Page Program (02h Command) Page Address Range 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0FFFFFh– 0FFF00h 0FFEFFh– 0FFE00h 0F F DF F h – 0F F D00h 0FFCFFh– 0FFC00h 0FFBFFh– 0FFB00h 0F F AF F h – 0F F A00h 0FF9FFh – 0FF900h 0FF8FFh – 0FF800h 0FF7FFh – 0FF700h 0FF6FFh – 0FF600h 0FF5FFh – 0FF500h 0FF4FFh – 0FF400h 0FF3FFh – 0FF300h 0FF2FFh – 0FF200h 0FF1FFh – 0FF100h 0FF0FFh – 0FF000h 0FEFFFh– 0FEF00h 0FEEFFh– 0FEE00h 0F E DF F h – 0F E D00h 0FECFFh– 0FEC00h 0FEBFFh– 0FEB00h 0F E AF F h – 0F E A00h 0FE9FFh– 0FE900h 0FE8FFh– 0FE800h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh – 001700h 0016FFh – 001600h 0015FFh – 001500h 0014FFh – 001400h 0013FFh – 001300h 0012FFh – 001200h 0011FFh – 001100h 0010FFh – 001000h 000FFFh – 000F00h 000EFFh – 000E00h 000DF F h – 000D00h 000CFFh – 000C00h 000BFFh – 000B00h 000AF F h – 000A00h 0009FFh – 000900h 0008FFh – 000800h 0007FFh – 000700h 0006FFh – 000600h 0005FFh – 000500h 0004FFh – 000400h 0003FFh – 000300h 0002FFh – 000200h 0001FFh – 000100h 0000FFh – 000000h 3674E–DFLASH–8/08 5 5 Page AT25DF081 www.DataSheet4U.com If the address specified by A23-A0 points to a memory location within a sector that is in the pro- tected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis- ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Block Erase CS SCK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 OPCODE ADDRESS BITS A23-A0 CCCCCCCCAAAAAA MSB MSB AAAAAA HIGH-IMPEDANCE 8.3 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been pre- viously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis- 3674E–DFLASH–8/08 11 11 Page

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