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PDF ADV7844 Data sheet ( Hoja de datos )
| Número de pieza | ADV7844 | |
| Descripción | Quad HDMI Fast Switching Receiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Quad HDMI Fast Switching Receiver with 12-Bit, 170 MHz
Video and Graphics Digitizer and 3D Comb Filter Decoder
ADV7844
FEATURES
Quad HDMI® 1.4 fast switching receiver
HDMI support
Audio return channel (ARC)
3D TV support
Content type bits
CEC 1.4-compatible
Extended colorimetry
HDMI 225 MHz receiver
Xpressview fast switching of HDMI ports
2 ARC interfaces for ARC support
SPDIF interface for ARC support
3D video format support, including frame packing 1080p
24 Hz, 720p 50 Hz, 720p 60 Hz
Full colorimetry support including sYCC601, Adobe RGB,
Adobe YCC 601
36-/30-bit Deep Color and 24-bit color support
HDCP 1.4 support with internal HDCP keys
5 V detect and hot plug assert for each HDMI port
Adaptive HDMI equalizer
Integrated CEC controller
HDMI repeater support
HDMI audio support including HBR and DSD
Advanced audio mute feature
Flexible digital audio output interfaces
Supports up to 5 S/PDIF outputs
Supports up to 4 I2S outputs
Video and graphics digitizer
Four 170 MHz, 12-bit ADCs
12-channel analog input mux
525i-/625i-component analog input
525p-/625p-component progressive scan support
720p-/1080i-/1080p-component HDTV support
Low refresh rates (24/25/30 Hz) support for 720p/1080p
Digitizes RGB graphics up to 1600 × 1200 at 60 Hz (UXGA)
SCART fast blank support
3D video decoder
NTSC/PAL/SECAM color standards support
NTSC/PAL 2D/3D motion detecting comb filter
Advanced time-base correction (TBC) with frame
synchronization
Interlaced-to-progressive conversion for 525i and 625i
IF compensation filters
Vertical peaking and horizontal peaking filters
Robust synchronization extraction for poor video source
Advanced VBI data slicer
General
Highly flexible 36-bit pixel output interface
Internal EDID RAM for HDMI and graphics
Dual STDI (standard identification) function support
Any-to-any, 3 × 3 color space conversion (CSC) matrix
2 programmable interrupt request output pins
Simultaneous analog processing and HDMI monitoring
APPLICATIONS
Advanced TVs
PDP HDTVs
LCD TVs (HDTV ready)
LCD/DLP® rear projection HDTVs
LCoS™ HDTVs
AVR video receivers
HDTV STBs with PVR
Projectors
FUNCTIONAL BLOCK DIAGRAM
SCART
CVBS
SDRAM
CVBS
48
SCART RGB
+ CVBS
CVBS
YC
SD/PS
YPbPr
HD YpbPr
GRAPHICS
RGB
HDMI 1
HDMI 2
HDMI 3
HDMI 4
S/PDIF
ARC_1±
ARC_2±
ADC
ADC
ADC
ADC
CVBS
SCART G
SCART B
SCART R
SDP
CVBS
3D YC
S-VIDEO
SCART
HS/VS
FIELD/DE
CLK
DATA
TMDS
DDC
TMDS
DDC
TMDS
DDC
TMDS
DDC
ARC
CP
Y/G YPbPr
525p/625p
Pb/B 720p/1080i
1080p/
Pb/R UXGA
RGB
HS/VS
FIELD/DE
CLK
DATA
36
DEEP
COLOR
HDMI Rx
FAST
SWITCH
HDCP
KEYS
4 I2S
S/PDIF
DSD
HBR
MCLK
SCLK
ADV7844
HS/VS
FIELD/DE
CLK
36-BIT
YCbCr/RGB
AUDIO
OUTPUT 5
MCLK
SCLK
TO AUDIO
PROCESSOR
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
1 page  
ADV7844
DETAILED FUNCTIONAL BLOCK DIAGRAM
Data Sheet
Figure 2. Detailed Functional Block Diagram
Rev. B | Page 4 of 32
5 Page 
ADV7844
Data Sheet
TIMING CHARACTERISTICS
Data and I2C Timing Characteristics
Table 5.
Parameter1
CLOCK AND CRYSTAL
Crystal Frequency, XTAL
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
I2C PORTS
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
SDA Setup Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Stop Condition Setup Time
TTX I2C PORTS
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
SDA Setup Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Stop Condition Setup Time
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark-Space Ratio
DATA AND CONTROL OUTPUTS2
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (CP)
Data Output Transition Time SDR (CP)
I2S PORT, MASTER MODE
SCLK Mark-Space Ratio
LRCLK Data Transition Time
LRCLK Data Transition Time
I2Sx Data Transition Time
I2Sx Data Transition Time
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
t11
t12
t13
t14
t15:t16
t17
t18
t19
t20
1 Guaranteed by characterization.
2 With the DLL block on output clock bypassed.
Test Conditions/Comments
End of valid data to negative clock edge
Negative clock edge to start of valid data
End of valid data to negative clock edge
Negative clock edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
End of valid data to negative SCLK edge
Negative SCLK edge to start of valid data
Min Typ
Max
10
12.825
28.63636
±50
110
170
400
600
1.3
600
600
100
1000
300
0.6
3.4
60
160
160
160
10
10 80
10 80
160
5
45:55
55:45
2.9 4.6
0.2 0.6
1.5 2.2
0.1 0.3
45:55
55:45
10
10
5
5
Unit
MHz
ppm
kHz
MHz
kHz
ns
μs
ns
ns
ns
ns
ns
μs
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
% duty cycle
ns
ns
ns
ns
% duty cycle
ns
ns
ns
ns
Rev. B | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADV7844.PDF ] | |
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