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PDF M24LR64-R Data sheet ( Hoja de datos )

Número de pieza M24LR64-R
Descripción 64 Kbit EEPROM
Fabricantes STMicroelectronics　
Logotipo STMicroelectronics Logotipo



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M24LR64-R
64 Kbit EEPROM with password protection & dual interface:
400 kHz I²C serial bus & ISO 15693 RF protocol at 13.56 MHz
Features
I²C interface
■ Two-wire I2C serial interface
supports 400 kHz protocol
■ Single supply voltage:
– 1.8 V to 5.5 V
■ Byte and Page Write (up to 4 bytes)
■ Random and Sequential Read modes
■ Self-timed programming cycle
■ Automatic address incrementing
■ Enhanced ESD/latch-up protection
Contactless interface
■ ISO 15693 and ISO 18000-3 mode 1 compliant
■ 13.56 MHz ±7k Hz carrier frequency
■ To tag: 10% or 100% ASK modulation using
1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse
position coding
■ From tag: load modulation using Manchester
coding with 423 kHz and 484 kHz subcarriers
in low (6.6 kbit/s) or high (26 kbit/s) data rate
mode. Supports the 53 kbit/s data rate with
Fast commands
■ Internal tuning capacitance: 27.5 pF
■ 64-bit unique identifier (UID)
■ Read Block & Write (32-bit Blocks)
Memory
■ 64 Kbit EEPROM organized into:
– 8192 bytes in I²C mode
– 2048 blocks of 32 bits in RF mode
■ Write time
– I²C: 5 ms (Max.)
– RF: 5.75 ms including the internal Verify
time
■ More than 1 Million write cycles in I2C mode
SO8 (MN)
150 mils width
UFDFPN8 (MB)
2 × 3 mm
TSSOP8 (DW)
■ More than 100 000 write cycles in RF mode
■ Multiple password protection in RF mode
■ Single password protection in I2C mode
■ More than 40-year data retention
■ Package
– ECOPACK2® (RoHS compliant and
Halogen-free)
April 2010
Doc ID 15170 Rev 9
1/126
www.st.com
1

1 page




M24LR64-R pdf
M24LR64-R
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Contents
19 Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
19.1 Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
20 Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20.1 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
20.2 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
21 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
22 Request processing by the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 68
23 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25.1 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
25.3 t3: VCD new request delay in the absence of a response from
the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
26 Commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
26.3 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
26.4 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
26.5 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
26.6 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
26.7 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
26.8 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
26.9 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 15170 Rev 9
5/126

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M24LR64-R arduino
M24LR64-R
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List of figures
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
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Figure 57.
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Figure 59.
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Figure 64.
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Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
M24LR64-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
M24LR64-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 67
Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Stay Quiet frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . 75
Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 77
Write Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 79
Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . 81
Select frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Reset to Ready frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . 83
Write AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 85
Lock AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 87
Write DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 89
Lock DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 91
Get System Info frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . . . . 93
Get Multiple Block Security Status frame exchange between VCD and M24LR64-R . . . . 95
Write-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 97
Lock-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . 99
Present-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . 101
Fast Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . 103
Fast Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 105
Fast Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . 107
Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . 109
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
M24LR64-R synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 117
UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead
2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 119
Doc ID 15170 Rev 9
11/126

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