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PDF M24L48512DA Data sheet ( Hoja de datos )
| Número de pieza | M24L48512DA | |
| Descripción | 4-Mbit (512K x 8) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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ESMT
www.DataSheet4U.com
M24L48512DA
PSRAM
4-Mbit (512K x 8)
Pseudo Static RAM
Features
• Advanced low power architecture
• High speed: 55 ns, 60 ns and 70 ns
• Wide voltage range: 2.7V to 3.6V
• Typical active current: 1mA @ f = 1 MHz
• Low standby power
• Automatic power-down when deselected
Functional Description
The M24L48512DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 512K words by 8 bits. Easy
memory expansion is provided by an active LOW Chip
Enable( CE1), an active HIGH Chip Enable (CE2), and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by taking Chip Enable One ( CE1) and Write
Enable ( WE )inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O15) is then
written into the location specified on the address pins (A0
through A18).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE1) and Output Enable ( OE ) inputs LOW
while forcing Write Enable ( WE ) HIGH and Chip Enable
Two(CE2) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected CE1
HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE1 LOW, CE2 HIGH, and WE
LOW).See the Truth Table for a complete description of read
and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
1/12
1 page  
ESMT
www.DataSheet4U.com
M24L48512DA
Switching Characteristics (Over the Operating Range)[7] (continued)
Prameter
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Description
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[8, 9]
WE HIGH to Low Z[8, 9]
–55
Min.
0
Max.
40
25
0
25
5
Switching Waveforms
Read Cycle 1 (Address Transition Controlled) [11, 12, 13]
–60
Min.
0
Max.
40
25
0
25
5
–70
Min.
0
Max.
45
25
0
25
5
Unit
ns
ns
ns
ns
ns
ns
Read Cycle 2 ( OE Controlled) [11, 13]
Notes:
12.Device is continuously selected. OE , CE = VIL.
13. WE is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
5/12
5 Page 
ESMT
Revision History
Revision
1.0
1.1
www.DataSheet4U.com
M24L48512DA
Date
2007.07.19
2008.07.04
Description
Original
1. Move Revision History to the last
2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V
3. Add Industrial grade
4. Add Avoid timing
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.1
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet M24L48512DA.PDF ] | |
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