|
|
PDF M24L416256SA Data sheet ( Hoja de datos )
| Número de pieza | M24L416256SA | |
| Descripción | 4-Mbit (256K x 16) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de M24L416256SA (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
ESMT
www.DataSheet4U.com
M24L416256SA
PSRAM
4-Mbit (256K x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.7V–3.6V
• Access time: 55 ns, 60 ns and 70 ns
• Ultra-low active power
— Typical active current: 1 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = fmax (70-ns speed)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The M24L416256SA is a high-performance CMOS Pseudo
static RAM organized as 256K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0through I/O15) are placed in a
high-impedance state when : deselected ( CE HIGH), outputs
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled ( BHE , BLE HIGH), or during a write
operation ( CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip
Enable( CE LOW) and Write Enable ( WE ) input LOW. If Byte
Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7) is written into the location specified on the
address pins(A0 through A17). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written into
the location specified on the address pins (A0 through A17).
Reading from the device is accomplished by taking Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 toI/O15. Refer to the truth table for a complete description
of read and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
1/14
1 page  
ESMT
AC Test Loads and Waveforms
www.DataSheet4U.com
M24L416256SA
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Switching Characteristics (Over the Operating Range)[10]
Unit
Ω
Ω
Ω
V
Prameter
Description
Read Cycle
tRC
tAA
tOHA
tACE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
tDOE OE LOW to Data Valid
tLZOE
OE LOW to Low Z[11, 13]
tHZOE
OE HIGH to High Z[11, 13]
tLZCE
CE LOW to Low Z[11, 13]
tHZCE
tDBE
tLZBE
CE HIGH to High Z[11, 13]
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[11, 13]
tHZBE
BLE / BHE HIGH to High-Z[11, 13]
tSK [14]
Address Skew
Write Cycle[12]
tWC Write Cycle Time
tSCE CE LOW to Write End
tAW Address Set-up to Write End
tHA Address Hold from Write End
tSA Address Set-up to Write Start
tPWE WE Pulse Width
–55
Min.
Max.
55
55
5
55
25
5
25
2
25
55
5
10
0
55
45
45
0
0
40
–60
Min.
Max.
60
60
8
60
25
5
25
2
25
60
5
10
5
60
45
45
0
0
40
–70
Min.
Max.
70
70
10
70
35
5
25
5
25
70
5
25
10
70
60
55
0
0
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ)/2, input pulse levels of 0V to V CC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test
Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
12. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK is
satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable
within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
5/14
5 Page 
ESMT
Package Diagram
48-ball VFBGA (6 x 8 x 1 mm)
www.DataSheet4U.com
M24L416256SA
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet M24L416256SA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M24L416256SA | 4-Mbit (256K x 16) Pseudo Static RAM | Elite Semiconductor Memory Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |