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PDF M24L28256DA Data sheet ( Hoja de datos )
| Número de pieza | M24L28256DA | |
| Descripción | 2-Mbit (256K x 8) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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ESMT
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M24L28256DA
PSRAM
2-Mbit (256K x 8)
Features
•Advanced low-power architecture
•High speed: 55 ns, 70 ns
•Wide voltage range: 2.7V to 3.3V
•Typical active current: 1 mA @ f = 1 MHz
•Low standby power
•Automatic power-down when deselected
Functional Description
The M24L28256DA is a high-performance CMOS pseudo
static RAM (PSRAM) organized as 256K words by 8 bits.
Easy memory expansion is provided by an active LOW Chip
Enable( CE 1) and active HIGH Chip Enable ( CE 2),and active
LOW Output Enable ( OE ).This device has an automatic
power-down feature that reduces power consumption
dramatically when deselected. Writing to the device is
accomplished by asserting Chip Enable One ( CE 1) and Write
Pseudo Static RAM
Enable ( WE ) inputs LOW and Chip Enable Two ( CE 2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A17).
Reading from the device is accomplished by asserting the
Chip Enable One ( CE 1) and Output Enable ( OE ) inputs
LOW while forcing Write Enable ( WE ) HIGH. And Chip
Enable Two ( CE 2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected ( CE 1
HIGH or CE2 LOW), the outputs are disabled ( OE HIGH), or
during write operation ( CE 1 LOW, CE2 HIGH, and WE
LOW). See the Truth Table for a complete description of read
and write modes.
Logic Block Diagram
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
1/10
1 page  
ESMT
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[11, 12, 13]
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M24L28256DA
Read Cycle 2 ( OE Controlled)[11, 13]
Notes:
12. Device is continuously selected. OE , CE 1=VIL and CE2 = VIH.
13. WE is HIGH for Read Cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2007
Revision : 1.0
5/10
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet M24L28256DA.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| M24L28256DA | 2-Mbit (256K x 8) Pseudo Static RAM | Elite Semiconductor Memory Technology |
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