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PDF M24L216128SA Data sheet ( Hoja de datos )
| Número de pieza | M24L216128SA | |
| Descripción | 2-Mbit (128K x 16) Pseudo Static RAM | |
| Fabricantes | Elite Semiconductor Memory Technology | |
| Logotipo |  |
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M24L216128SA
PSRAM
2-Mbit (128K x 16)
Features
• Wide voltage range: 2.7V–3.6V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
— Typical active current: 1mA @ f = 1 MHz
— Typical active current: 14 mA @ f = fmax (For 55-ns)
—Typical active current: 8 mA @ f = fmax (For 70-ns)
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The M24L216128SA is a high-performance CMOS Pseudo
Static RAM organized as 128K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( CE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when the chip is deselected ( CE
HIGH), or when the outputs are disabled ( OE HIGH), or
Logic Block Diagram
Pseudo Static RAM
when both Byte High Enable and Byte Low Enable are
disabled ( BHE , BLE HIGH), or during a write operation
( CE LOW and WE LOW).
Writing to the device is accomplished by asserting Chip
Enable ( CE LOW) and Write Enable ( WE ) input LOW. If
Byte Low Enable ( BLE ) is LOW, then data from I/O pins (I/O0
through I/O7), is written into the location specified on the
address pins (A0 through A16). If Byte High Enable ( BHE ) is
LOW, then data from I/O pins (I/O8 through I/O15) is written
into the location specified on the address pins (A0 through
A16).
Reading from the device is accomplished by asserting Chip
Enable ( CE LOW) and Output Enable ( OE ) LOW while
forcing the Write Enable ( WE ) HIGH. If Byte Low Enable
( BLE ) is LOW, then data from the memory location specified
by the address pins will appear on I/O0 to I/O7. If Byte High
Enable( BHE ) is LOW, then data from memory will appear on
I/O8 to I/O15. Refer to the truth table for a complete description
of read and write modes.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
1/14
1 page  
ESMT
AC Test Loads and Waveforms
M24L216128SAwww.DataSheet4U.com
Parameters
R1
R2
RTH
VTH
3.0V VCC
22000
22000
11000
1.50
Switching Characteristics Over the Operating Range[10]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
tLZBE
tHZBE
tSK[14]
Write Cycle[12]
tWC
tSCE
tAW
tHA
tSA
tPWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z[11, 13]
OE HIGH to High Z[11, 13]
CE LOW to Low Z[11, 13]
CE HIGH to High Z[11, 13]
BLE / BHE LOW to Data Valid
BLE / BHE LOW to Low Z[11, 13]
BLE / BHE HIGH to HIGH Z[11, 13]
Address Skew
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
-55 [14]
Min.
Max.
55[14]
5
5
2
5
55
55
25
25
25
55
10
0
55
45
45
0
0
40
Unit
Ω
Ω
Ω
V
-70
Min. Max.
70
70
10
70
35
5
25
5
25
70
5
25
10
70
60
60
0
0
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
10. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC(typ)/2, input pulse levels of 0V to VCC(typ.), and output loading of the specified IOL/IOH as shown in the “AC Test
Loads and Waveforms” section.
11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.12.The internal Write
time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to
initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing
should be referenced to the edge of the signal that terminates the write.
13. High-Z and Low-Z parameters are characterized and are not 100% tested.
14. To achieve 55-ns performance, the read access should be CE controlled. In this case tACE is the critical parameter and tSK
is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be
stable within 10 ns after the start of the read cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
5/14
5 Page 
ESMT
Package Diagram
M24L216128SAwww.DataSheet4U.com
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.2
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet M24L216128SA.PDF ] | |
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