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PDF XC800 Data sheet ( Hoja de datos )
| Número de pieza | XC800 | |
| Descripción | Microcontroller Family Architecture and Instruction Set | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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User’s Manual, V 0.1, Jan 2005
www.DataSheet4U.com
XC800
Microcontroller Family
Architecture and Instruction Set
Microcontrollers
Never stop thinking.
1 page  
XC800www.DataSheet4U.com
Table of Contents
Page
1
1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.4
1.3.4.1
1.3.4.2
1.4
Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Memory Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Extension Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Extension Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Internal Data Memory XRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Function Register Extension by Mapping . . . . . . . . . . . . . . . . 7
Special Function Register Extension by Paging . . . . . . . . . . . . . . . . . 8
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
2.1.10
2.1.11
2.2
2.3
2.3.1
2.3.2
2.4
2.5
CPU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Memory Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Timer/Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
On-Chip Debug Support Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Basic Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt Source and Vector Address . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Service Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3
3.1
3.2
3.2.1
3.2.2
CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Accessing External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Accessing External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
User’s Manual, V 0.1
I-1
2005-01
5 Page 
XC800www.DataSheet4U.com
Fundamental Structure
1.3.2 Program Memory
Up to 1 Mbyte of synchronous or asynchronous internal and/or external program
memory is supported. Program memory extension, if supported by the XC800 derivative,
is accomplished with a 4-bit Current Bank pointer (CB). The program code is fetched
from the 64-Kbyte block pointed to by CB. The minimum supported code space is
therefore 64 Kbytes.
If the internal program memory is used, the EA (External Access) pin must be held at
high level. With EA held high, the microcontroller executes instructions internally unless
the address (Program Counter) is outside the range of the internal program memory. In
this case, dynamic code fetch from internal and external program memory is supported
if the external memory bus is available on the derivative. If the EA pin is held at low level,
the microcontroller executes program code from external program memory, instead of
from internal memory. The general exception is for accesses to address ranges of the
active Boot ROM, internal XRAM and code-space data (e.g., Data Flash), where fetch is
always from the internal memory regardless of the status of EA pin.
Most XC800 derivatives include a section for Boot ROM code, the size of which depends
on the derivative. Usually, the Boot ROM code is executed first after reset where the Boot
ROM is mapped starting from base address 0000H of the code space. The Boot ROM
code will switch the memory mapping so that before control is passed to the user code,
the standard memory map (of the derivative) is active where user code could run starting
from address 0000H.
For program memory implemented as RAM, the XC800 core supports write to program
memory with the instruction MOVC @(DPTR++),A. This is generally supported by the
XC800 derivatives for writes to internal memory only.
1.3.3 Data Memory
The data memory space consists of internal and external memory portions. The internal
data memory area is addressed using 8-bit addresses. The external data memory and
the internal XRAM data memory are addressable by 8-bit or 16-bit indirect address with
‘MOVX’, additionally with up to 4-bit for selection of extended memory bank (maximum
1 Mbyte).
1.3.3.1 Internal Data Memory
The internal data memory is divided into two physically separate and distinct blocks: the
256-byte RAM and the 128-byte SFR area. While the upper 128 bytes of RAM and the
SFR area share the same address locations, they are accessed through different
addressing modes. The lower 128 bytes of RAM can be accessed through either direct
or register indirect addressing while the upper 128 bytes of RAM can be accessed
through register indirect addressing only. The special function registers are accessible
through direct addressing.
User’s Manual, V 0.1
1-5
2005-01
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XC800.PDF ] | |
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