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PDF PBRN113E Data sheet ( Hoja de datos )
| Número de pieza | PBRN113E | |
| Descripción | NPN 800 mA 40 V BISS RETs | |
| Fabricantes | NXP Semiconductors | |
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PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
Rev. 01 — 1 March 2007
Product data sheet
1. Product profile
1.1 General description
800 mA NPN low VCEsat Breakthrough In Small Signal (BISS) Resistor-Equipped
Transistors (RET) family in small plastic packages.
Table 1. Product overview
Type number
Package
NXP
PBRN113EK
SOT346
PBRN113ES[1]
SOT54
PBRN113ET
SOT23
JEITA
SC-59A
SC-43A
-
[1] Also available in SOT54A and SOT54 variant packages (see Section 2).
JEDEC
TO-236
TO-92
TO-236AB
1.2 Features
I 800 mA output current capability
I High current gain hFE
I Built-in bias resistors
I Simplifies circuit design
I Low collector-emitter saturation voltage
VCEsat
I Reduces component count
I Reduces pick and place costs
I ±10 % resistor ratio tolerance
1.3 Applications
I Digital application in automotive and
industrial segments
I Medium current peripheral driver
I Switching loads
1.4 Quick reference data
Table 2.
Symbol
VCEO
IO
Quick reference data
Parameter
Conditions
collector-emitter voltage
open base
output current
PBRN113EK, PBRN113ET
PBRN113ES
Min Typ Max Unit
- - 40 V
[1]
- - 600 mA
- - 800 mA
1 page  
NXP Semiconductors
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PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
800
Ptot
(mW)
600
006aaa999
400
200
0
−75
−25
25
75 125 175
Tamb (°C)
FR4 PCB, standard footprint
Fig 2. Power derating curve for SOT54 (SC-43A/TO-92)
6. Thermal characteristics
Table 7.
Symbol
Rth(j-a)
Thermal characteristics
Parameter
Conditions
thermal resistance from junction in free air
to ambient
PBRN113EK, PBRN113ET
Rth(j-sp)
PBRN113ES
thermal resistance from junction
to solder point
PBRN113EK, PBRN113ET
Min Typ Max Unit
[1] - - 500 K/W
[2] - - 338 K/W
[3] - - 219 K/W
[1] - - 179 K/W
- - 105 K/W
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Device mounted on an FR4 PCB, single-sided copper, tin-plated, mounting pad for collector 1 cm2.
[3] Device mounted on a ceramic PCB, Al2O3, standard footprint.
PBRN113E_SER_1
Product data sheet
Rev. 01 — 1 March 2007
© NXP B.V. 2007. All rights reserved.
5 of 17
5 Page 
NXP Semiconductors
8. Package outline
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PBRN113E series
NPN 800 mA, 40 V BISS RETs; R1 = 1 kΩ, R2 = 1 kΩ
3.1
2.7
3
1.3
1.0
0.6
0.2
4.2
3.6
0.45
0.38
3.0 1.7
2.5 1.3
1
Dimensions in mm
1.9
2
0.50
0.35
0.26
0.10
04-11-11
4.8
4.4
5.2
5.0
Dimensions in mm
14.5
12.7
0.48
0.40
1
2
2.54
3 1.27
04-11-16
Fig 13. Package outline SOT346 (SC-59A/TO-236)
Fig 14. Package outline SOT54 (SC-43A/TO-92)
4.2
3.6
3 max
4.8
4.4
5.2
5.0
Dimensions in mm
14.5
12.7
Fig 15. Package outline SOT54A
0.45
0.38
0.48
0.40
1
2
5.08
2.54
3
04-06-28
4.2
3.6
2.5
max
4.8
4.4
5.2
5.0
Dimensions in mm
14.5
12.7
0.45
0.38
1.27
0.48
0.40
1
2
2.54
3 1.27
05-01-10
Fig 16. Package outline SOT54 variant
2.5 1.4
2.1 1.2
3.0
2.8
3
1.1
0.9
0.45
0.15
1
Dimensions in mm
Fig 17. Package outline SOT23 (TO-236AB)
1.9
2
0.48
0.38
PBRN113E_SER_1
Product data sheet
Rev. 01 — 1 March 2007
0.15
0.09
04-11-04
© NXP B.V. 2007. All rights reserved.
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