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PDF P89LPC971 Data sheet ( Hoja de datos )
| Número de pieza | P89LPC971 | |
| Descripción | 8-bit microcontroller | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
2 kB/4 kB/8 kB wide-voltage byte-erasable flash
Rev. 02 — 27 April 2010
Product data sheet
1. General description
The P89LPC970/971/972 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC970/971/972 in order to reduce component
count, board space, and system cost.
2. Features and benefits
2.1 Principal features
2 kB/4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and
64-byte pages. Single-byte erasing allows any byte(s) to be used as non-volatile data
storage.
256-byte RAM data memory.
Two analog comparators with selectable inputs and reference source.
Five 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I2C-bus
communication port.
SPI communication port (pin remap).
High-accuracy internal RC oscillator option 7.373 MHz calibrated to ±1 %, with clock
doubler option, allows operation without external oscillator components. The RC
oscillator option is selectable and fine tunable.
Watchdog timer with separate on-chip oscillator, nominal 400 kHz/25 kHz, calibrated to
±10 % at 400 kHz, requiring no external components. The watchdog prescaler is
selectable from eight values.
Pin remap for UART, I2C-bus and SPI.
2.4 V to 5.5 V VDD operating range.
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
20-pin TSSOP and DIP packages with 15 I/O pins minimum and up to 18 I/O pins
while using on-chip oscillator and reset options.
1 page  
NXP Semiconductors
5. Functional diagram
www.DataSheet4U.com
P89LPC970/971/972
8-bit microcontroller with accelerated two-clock 80C51 core
SPICLK(1)
T2
T3
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
XTAL1
PORT 0
PORT 3
(1) For pin remap
Fig 2. Functional diagram
VDD VSS
P89LPC970/
971/972
PORT 1
TXD
RXD
T0
INT0
INT1
RST
MISO(1)
T3EX
T2EX
SCL
SDA
T4EX
MOSI(1)
T4
SS(1)
002aae551
P89LPC97X_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 April 2010
© NXP B.V. 2010. All rights reserved.
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Table 4. Special function registers
* indicates SFRs that are bit addressable.
Name
Description
SFR
addr.
Bit functions and addresses
MSB
LSB
Reset value
Hex Binary
Bit address E7 E6 E5 E4 E3 E2 E1 E0
ACC* Accumulator
E0H
00 0000 000
0
AUXR1 Auxiliary
function register
A2H
CLKLP EBRR
ENT1
ENT0
SRST
0
- DPS 00 0000 00x0
Bit address F7 F6 F5 F4 F3 F2 F1 F0
B* B register
F0H
00 0000 000
0
BRGR0[1] Baud rate
generator 0 rate
low
BEH
00 0000 000
0
BRGR1[1] Baud rate
generator 0 rate
high
BFH
00 0000 000
0
BRGCO Baud rate
BDH
-
-
-
-
-
- SBRGS BRGEN 00[1] xxxx xx00
N generator 0
control
CMP1
Comparator 1
control register
ACH
-
-
CE1
CP1
CN1
OE1
CO1
CMF1 00[2] xx00 0000
CMP2
Comparator 2
control register
ADH
-
-
CE2
CP2
CN2
OE2
CO2
CMF2 00[2] xx00 0000
DIVM
CPU clock
divide-by-M
control
95H
00 0000 000
0
DPTR
Data pointer
(2 bytes)
DPH Data pointer
high
83H
00 0000 000
0
DPL Data pointer low 82H
00 0000 000
0
FMADRH Program flash
address high
E7H
00 0000 000
0
FMADRL Program flash
address low
E6H
00 0000 000
0
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet P89LPC971.PDF ] | |
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