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PDF IMX51A Data sheet ( Hoja de datos )
| Número de pieza | IMX51A | |
| Descripción | i.MX51A Automotive and Infotainment Applications Processors | |
| Fabricantes | Freescale Semiconductor | |
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: IMX51AEC
Rev. 6, 10/2012
IMX51A
i.MX51A Automotive and
Infotainment Applications
Processors
Package Information
Plastic Package
Case 2017 19 x 19 mm, 0.8 mm pitch
Ordering Information
See Table 1 on page 2 for ordering information.
1 Introduction
The MCIMX51A (i.MX51A) Automotive Infotainment
Processor represents Freescale Semiconductor’s latest
addition to a growing family of multimedia focused
products offering high performance processing with a
high degree of functional integration, aimed at the
growing automotive infotainment market. This device
includes two graphics processors, 720p video
processing, dual display, and many I/Os.
The i.MX51A processor features Freescale’s advanced
implementation of the ARM Cortex A8™ core, targeting
speeds up to 600 MHz with 200 MHz I/O bus clock
DDR2 and mobile DDR. This device is well-suited for
graphics rendering for HMI and navigation, high
performance speech processing with large databases,
video processing and display, audio playback and
ripping, and many other applications.
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 2
1.2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Special Signal Considerations . . . . . . . . . . . . . . . 11
3. IOMUX Configuration for Boot Media . . . . . . . . . . . . . . . 13
3.1. NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2. SD/MMC IOMUX Pin Configuration . . . . . . . . . . . 14
3.3. I2C IOMUX Pin Configuration . . . . . . . . . . . . . . . . 14
3.4. eCSPI/CSPI IOMUX Pin Configuration . . . . . . . . 15
3.5. Wireless External Interface Module (WEIM) . . . . 15
3.6. UART IOMUX Pin Configuration . . . . . . . . . . . . . 15
3.7. USB-OTG IOMUX Pin Configuration . . . . . . . . . . 15
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . 16
4.2. Supply Power-Up/Power-Down Requirements and
Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3. I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4. Output Buffer Impedance Characteristics . . . . . . 29
4.5. I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 33
4.6. Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.7. External Peripheral Interfaces . . . . . . . . . . . . . . . 72
5. Package Information and Contact Assignments . . . . . 151
5.1. 19 x 19 mm Package Information . . . . . . . . . . . . 151
5.2. 19 x 19 mm, 0.8 Pitch Ball Map . . . . . . . . . . . . . 169
6. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
© 2012 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name Subsystem
Brief Description
EMI External
Connectivity The EMI is an external and internal memory interface. It performs arbitration
Memory
Peripherals between multi-AXI masters to multi-memory controllers, divided into four major
Interface
channels: fast memories (Mobile DDR, DDR2) channel, slow memories
(NOR-FLASH/PSRAM/NAND-FLASH and so on) channel, internal memory
(RAM, ROM) channel and graphical memory (GMEM) Channel.
In order to increase the bandwidth performance, the EMI separates the buffering
and the arbitration between different channels so parallel accesses can occur.
By separating the channels, slow accesses do not interfere with fast accesses.
EMI features:
• 64-bit and 32-bit AXI ports
• Enhanced arbitration scheme for fast channel, including dynamic master
priority, and taking into account which pages are open or closed and what
type (Read or Write) was the last access
• Flexible bank interleaving
• Supports 16/32-bit Mobile DDR up to 200 MHz SDCLK (mDDR400)
• Supports 16/32-bit (Non-Mobile) DDR2 up to 200 MHz SDCLK (DDR2-400)
• Supports up to 2 Gbit Mobile DDR memories
• Supports 16-bit (in muxed mode only) PSRAM memories (sync and async
operating modes), at slow frequency, for debugging purposes
• Supports 32-bit NOR-Flash memories (only in muxed mode), at slow
frequencies for debugging purposes
• Supports 4/8-ECC, page sizes of 512 Bytes, 2 Kbytes and 4 Kbytes
• NAND-Flash (including MLC)
• Multiple chip selects
• Enhanced Mobile DDR memory controller, supporting access latency hiding
• Supports watermarking for security (Internal and external memories)
• Supports Samsung OneNAND™ (only in muxed I/O mode)
EPIT-1
EPIT-2
Enhanced
Periodic
Interrupt
Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the EPIT is
enabled by software. It is capable of providing precise interrupts at regular
intervals with minimal processor intervention. It has a 12-bit prescaler for division
of input clock frequency to get the required time setting for the interrupts to occur,
and counter values can be programmed on the fly.
eSDHC-1
eSDHC-2
eSDHC-3
Enhanced
Multi-Media
Card/
Secure Digital
Host
Controller
Connectivity
Peripherals
The features of the eSDHC module, when serving as host, include the following:
• Conforms to SD Host Controller Standard Specification version 2.0
• Compatible with the MMC System Specification version 4.2
• Compatible with the SD Memory Card Specification version 2.0
• Compatible with the SDIO Card Specification version 1.2
• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC and MMC RS cards
• Configurable to work in one of the following modes:
—SD/SDIO 1-bit, 4-bit
—MMC 1-bit, 4-bit, 8-bit
• Full-/high-speed mode
• Host clock frequency variable between 32 kHz to 52 MHz
• Up to 200 Mbps data transfer for SD/SDIO cards using four parallel data lines
• Up to 416 Mbps data transfer for MMC cards using eight parallel data lines
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
5
5 Page 
Features
Table 2. i.MX51A Digital and Analog Modules (continued)
Block
Mnemonic
Block Name Subsystem
Brief Description
WDOG-2
(TZ)
Watch Dog
(TrustZone)
Timer
Peripherals
The TrustZone Watchdog (TZ WDOG) timer module protects against TrustZone
starvation by providing a method of escaping normal mode and forcing a switch
to the TZ mode. TZ starvation is a situation where the normal OS prevents
switching to the TZ mode. This situation should be avoided, as it can
compromise the system’s security. Once the TZ WDOG module is activated, it
must be serviced by TZ software on a periodic basis. If servicing does not take
place, the timer times out. Upon a time-out, the TZ WDOG asserts a TZ mapped
interrupt that forces switching to the TZ mode. If it is still not served, the TZ
WDOG asserts a security violation signal to the CSU. The TZ WDOG module
cannot be programmed or deactivated by a normal mode SW.
XTALOSC Crystal
Clocking
Oscillator I/F
The XTALOSC module allows connectivity to an external crystal.
2.1 Special Signal Considerations
Table 3 lists special signal considerations for the i.MX51. The signal names are listed in alphabetical order.
The package contact assignments are found in Section 5, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX51 Multimedia Applications Processor
Reference Manual (MCIMX51RM).
Table 3. Special Signal Considerations
Signal Name
CKIH1, CKIH2
CLK_SS
COMP
FASTR_ANA and
FASTR_DIG
GPANAIO
Remarks
Inputs feeding CAMPs (Clock Amplifiers) that have on-chip ac coupling precluding the need for
external coupling capacitors. The CAMPs are enabled by default, but the main clocks feeding the
on-chip clock tree are sourced from XTAL/EXTAL by default. Optionally, the use of a low jitter
external oscillators to feed CKIH1 or CKIH2 (while not required) can be an advantage if low jitter
or special frequency clock sources are required by modules driven by CKIH1 or CKIH2. See CCM
chapter in the i.MX51 Multimedia Applications Processor Reference Manual (MCIMX51RM) for
details on the respective clock trees.
After initialization, the CAMPs could be disabled (if not used) by CCM registers (CCR CAMPx_EN
field). If disabled, the on-chip CAMP output is low; the input is irrelevant. If unused, the user should
tie CKIH1/CKIH2 to GND for best practice.
Clock Source Select is the input that selects the default reference clock source providing input to
the DPLLs. To use a reference in the megahertz range per Table 8, tie CLK_SS to GND to select
EXTAL/XTAL. To use a reference in the kilohertz range per Table 59, tie CLK_SS to NVCC_PER3
to select CKIL. After initialization, the reference clock source can be changed (initial setting is
overwritten).
Note: Because this input has a keeper circuit, Freescale recommends tying this input to directly
to GND or NVCC_PER3. If a series resistor is used its value must be ≤ 4.7 kΩ.
The user should bypass this reference with an external 0.1 µF capacitor tied to GND. If TV OUT is
not used, float the COMP contact and ensure the DACs are powered down.
Note: Previous engineering samples required this reference to be bypassed to a positive supply.
These signals are reserved for Freescale manufacturing use only. User must tie both connections
to GND.
This signal is reserved for Freescale manufacturing use only. Users should float this output.
i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
Freescale Semiconductor
11
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