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PDF AD9553 Data sheet ( Hoja de datos )
| Número de pieza | AD9553 | |
| Descripción | Flexible Clock Translator | |
| Fabricantes | Analog Devices | |
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Flexible Clock Translator for GPON, Base
Station, SONET/SDH, T1/E1, and Ethernet
AD9553
FEATURES
Input frequencies from 8 kHz to 710 MHz
Output frequencies up to 810 MHz LVPECL and LVDS (up to
200 MHz for CMOS output)
Preset pin-programmable frequency translation ratios cover
popular wireline and wireless frequency applications,
including xDSL, T1/E1, BITS, SONET, and Ethernet
Arbitrary frequency translation ratios via SPI port
On-chip VCO
Accepts a crystal resonator for holdover applications
Two single-ended (or one differential) reference input(s)
Two output clocks (independently programmable as LVDS,
LVPECL, or CMOS)
SPI-compatible, 3-wire programming interface
Single supply (3.3 V)
Very low power: <450 mW (under most conditions)
Small package size (5 mm × 5 mm)
Exceeds Telcordia GR-253-CORE jitter generation, transfer,
and tolerance specifications
APPLICATIONS
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Extremely flexible frequency translation for SONET/SDH,
Ethernet, Fibre Channel, DRFI/DOCSIS, and
PON/EPON/GPON
Wireless infrastructure
Test and measurement (including handheld devices)
GENERAL DESCRIPTION
The AD9553 is a phase-locked loop (PLL) based clock translator
designed to address the needs of passive optical networks (PON)
and base stations. The device employs an integer-N PLL to
accommodate the applicable frequency translation requirements.
The user supplies up to two single-ended input reference signals or
one differential input reference signal via the REFA and REFB
inputs. The device supports holdover applications by allowing the
user to connect a 25 MHz crystal resonator to the XTAL input.
The AD9553 is pin programmable, providing a matrix of standard
input/output frequency translations from a list of 15 possible input
frequencies to a list of 52 possible output frequency pairs (OUT1
and OUT2). The device also has a 3-wire SPI interface, enabling
the user to program custom input-to-output frequency translations.
The AD9553 output drivers are compatible with LVPECL, LVDS,
or single-ended CMOS logic levels, although the AD9553 is
implemented in a strictly CMOS process.
The AD9553 operates over the extended industrial temperature
range of −40°C to +85°C.
REFA
REFB
XTAL
BASIC BLOCK DIAGRAM
AD9553
INPUT
FREQUENCY
SOURCE
SELECTOR
PLL
OUTPUT
CIRCUITRY
PIN-DEFINED AND SERIAL PROGRAMMING
OUT2
OUT1
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
1 page  
AD9553
RESET PIN
Table 4.
Parameter
INPUT CHARACTERISTICS1
Input Voltage High, VIH
Input Voltage Low, VIL
Input Current High, IINH
Input Current Low, IINL
MINIMUM PULSE WIDTH LOW
Min Typ Max Unit
1.96
0.3
31
150
V
0.85 V
12.5 µA
43 µA
µs
1 The RESET pin has a 100 kΩ internal pull-up resistor.
Test Conditions/Comments
Tested with an active source driving the RESET pin
REFERENCE CLOCK INPUT CHARACTERISTICS
Table 5.
Parameter
DIFFERENTIAL INPUT
Input Frequency Range
Min Typ
0.008
Max
250
710
Common-Mode Internally Generated
Input Voltage
Differential Input Voltage Sensitivity
613
250
692 769
Differential Input Resistance
Differential Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
CMOS SINGLE-ENDED INPUT
Input Frequency Range
Input High Voltage
Input Low Voltage
Input Threshold Voltage
Input High Current
Input Low Current
Input Capacitance
Duty Cycle
Pulse Width Low
Pulse Width High
×2 FREQUENCY MULTIPLIER
5
3
1.6
1.6
0.64
0.64
0.008
1.62
1.0
200
0.52
0.04
0.03
3
2
2
125
Unit
MHz
MHz
mV
mV p-p
kΩ
pF
ns
ns
ns
ns
MHz
V
V
V
µA
µA
pF
ns
ns
MHz
Test Conditions/Comments
Assumes minimum LVDS input level and requires
bypassing of the divide-by-5 divider and ×2 multiplier
Use ac coupling to preserve the internal dc bias of the
differential input
Requires ac coupling; can accommodate single-ended
input by ac grounding unused input; the instantaneous
voltage on either pin must not exceed the 3.3 V dc supply
rails
Pulse width high and pulse width low specifications
establish the bounds for duty cycle
Up to 250 MHz
Up to 250 MHz
Beyond 250 MHz, up to 710 MHz
Beyond 250 MHz, up to 710 MHz
When ac coupling to the input receiver, the user must dc
bias the input to 1 V; the single-ended CMOS input is 3.3 V
compatible
Pulse width high and pulse width low establish the
bounds for duty cycle
To avoid excessive reference spurs, the ×2 multiplier
requires 48% to 52% duty cycle; reference clock input
frequencies greater than 125 MHz require the use of the
divide-by-5 divider
Rev. A | Page 4 of 44
5 Page 
AD9553
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Y4 1
Y5 2
A0 3
A1 4
A2 5
A3 6
REFA 7
REFB/REFA 8
PIN 1
INDICATOR
AD9553
TOP VIEW
(Not to Scale)
24 GND
23 OUT2
22 OUT2
21 VDD
20 LOCKED
19 LDO
18 VDD
17 LDO
Table 13. Pin Function Descriptions
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration
Pin No.
Mnemonic Type1 Description
29, 30, 31,
32, 1, 2
Y0, Y1, Y2, Y3, I
Y4, Y5
Control Pins. These pins select one of 52 preset output frequency combinations for OUT1 and OUT2. Note
that when all six control pins are Logic 0, SPI programming is active.
3, 4, 5, 6
A0, A1, A2,
A3
I
Control Pins. These pins select one of 15 preset input reference frequencies. Note that when all four control
pins are Logic 0, SPI programming is active.
7
REFA
I Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively, this pin is
the noninverted part of a differential clock input signal.
8
REFB/REFA I
Reference Clock Input. Connect this pin to a single-ended active clock input signal. Alternatively, this pin is
the inverted part of a differential clock input signal.
9, 10 XTAL
I Crystal Resonator Input. Connect a crystal resonator across these pins. Alternatively, connect a single-ended
clock source (CMOS compatible) to either input pin (let the unused pin float). When using the preset
input/output frequencies via the Y5 to Y0 and A3 to A0 pins, the crystal must have a resonant frequency of
25 MHz with a specified load capacitance of 10 pF.
11
SEL REFB
I
Control Pin. This pin allows manual selection of REFA (Logic 0) or REFB (Logic 1) as the active reference
assuming that the desired reference signal is present. Note that this pin is nonfunctional when
Register 0x29[5] = 1.
12
OM2/CS
I
Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM2) with an
internal 40 kΩ pull-up resistor. The OM2 pin, in conjunction with the OM0 and OM1 pins, allows the user to
select one of eight output configurations (see Table 21). In SPI mode, this pin is an active low chip select (CS)
with no internal pull-up resistor.
13
OM1/SCLK I
Digital Input. When the device is not in SPI mode, this pin is an output mode control pin (OM1) with an
internal 40 kΩ pull-up resistor. The OM1 pin, in conjunction with the OM0 and OM2 pins, allows the user to
select one of eight output configurations (see Table 21). In SPI mode, this pin is the serial data clock (SCLK)
with no internal pull-up resistor.
14 OM0/SDIO I/O Digital Input/Output. When the device is not in SPI mode, this pin is an input only and functions as an
output mode control pin (OM0) with an internal 40 kΩ pull-up resistor. The OM0 pin, in conjunction with the
OM1 and OM2 pins, allows the user to select one of eight output configurations (see Table 21). In SPI mode,
this pin is the serial data input/output (SDIO) with no internal pull-up resistor.
15
RESET
I Reset Internal Logic. This is a digital input pin. This pin is active low with a 100 kΩ internal pull-up resistor
and resets the internal logic to default states (see the Automatic Power-On Reset section).
16
FILTER
I/O Loop Filter Node for the PLL. Connect external loop filter components (see Figure 30) from this pin to Pin 17 (LDO).
17, 19
LDO
P/O LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to ground.
18, 21, 28 VDD
P Power Supply Connection: 3.3 V Analog Supply.
20
LOCKED
O Active High Locked Status Indicator for the PLL.
26, 22
OUT1, OUT2 O
Complementary Square Wave Clocking Outputs.
27, 23
OUT1, OUT2 O
Square Wave Clocking Outputs.
24, 25
GND
P Ground.
Not EP
Applicable
Exposed Pad. The exposed die pad must be connected to GND.
1 I = input, I/O = input/output, O = output, P = power, and P/O = power/output.
Rev. A | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9553.PDF ] | |
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