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PDF VN920DB5-E Data sheet ( Hoja de datos )

Número de pieza VN920DB5-E
Descripción High-side driver
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! VN920DB5-E Hoja de datos, Descripción, Manual

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VN920DB5-E
High-side driver
Features
Type
VN920DB5-E
RDS(on)
18 mΩ
IOUT
30 A
VCC
36 V
ECOPACK®: lead free and RoHS compliant
Automotive Grade: compliance with AEC
guidelines
Very low standby current
CMOS compatible input
Proportional load current sense
Current sense disable
Thermal shutdown protection and diagnosis
Undervoltage shutdown
Overvoltage clamp
Load current limitation
P2PAK
Description
The VN920DB5-E is a monolithic device designed
in STMicroelectronics™ VIPower™ M0-3
technology. The VN920DB5-E is intended for
driving any type of load with one side connected
to ground. The active VCC pin voltage clamp
protects the device against low energy spikes
(see ISO7637 transient compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protects the
device against overload. The device detects the
open-load condition in both the on-state and
off-state. In the off-state the device detects if the
output is shorted to VCC. The device automatically
turns-off in the case where the ground pin
becomes disconnected.
Table 1. Device summary
Package
P2PAK
May 2010
Tube
VN920DB5-E
Order codes
Tape and reel
VN920DB5TR-E
Doc ID 17493 Rev 1
1/26
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Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
VCC
GND
VCC
CLAMP
INPUT
LOGIC
STATUS
OVERTEMPERATURE
DETECTION
OVERVOLTAGE
DETECTION
UNDERVOLTAGE
DETECTION
Power CLAMP
DRIVER
CURRENT LIMITER
ON-STATE OPEN-LOAD
DETECTION
OFF-STATE OPEN-LOAD
AND
OUTPUT SHORTED
DETECTION
TO
VCC
OUTPUT
Figure 2. Configuration diagram (top view)
5 OUTPUT
4 STATUS
3 VCC
2 INPUT
1 GND
P2PAK
Table 2. Suggested connections for unused and not connected pins
Connection / pin
Status
N.C.
Output
Input
Floating
To ground
XXX
X
X Through 10 KΩ resistor
Doc ID 17493 Rev 1
5/26

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Electrical specifications
Table 12. Truth table
Conditions
Normal operation
Current limitation
Overtemperature
Undervoltage
Overvoltage
Output voltage > VOL
Output current < IOL
Input
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
Output
L
H
L
X
X
L
L
L
L
L
L
H
H
L
H
Status
H
H
H
(Tj < TTSD) H
(Tj > TTSD) L
H
L
X
X
H
H
L
H
H
L
Table 13. Electrical transient requirements
ISO T/R
7637/1
test pulse
I
Test level
II III IV Delays and impedance
1
- 25 V(1)
- 50 V(1)
- 75 V(1)
- 100 V(1)
2 ms,10 Ω
2
+ 25 V(1)
+ 50 V(1)
+ 75 V(1) + 100 V(1)
0.2 ms, 10 Ω
3a
- 25 V(1)
- 50 V(1)
- 100 V(1) - 150 V(1)
0.1 µs, 50 Ω
3b
+ 25 V(1)
+ 50 V(1)
+ 75 V(1) + 100 V(1)
0.1 µs, 50 Ω
4
- 4 V(1)
- 5 V(1)
- 6 V(1)
- 7 V(1)
100 ms, 0.01 Ω
5 + 26.5 V(1) + 46.5 V(2) + 66.5 V(2) + 86.5 V(2)
400 ms, 2 Ω
1. All functions of the device are performed as designed after exposure to disturbance.
2. One or more functions of the device is not performed as designed after exposure and cannot be returned to
proper operation without replacing the device.
Doc ID 17493 Rev 1
11/26

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