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PDF CDB4382 Data sheet ( Hoja de datos )

Número de pieza CDB4382
Descripción 192 kHz 8-Channel D/A Converter
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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No Preview Available ! CDB4382 Hoja de datos, Descripción, Manual

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CS4382
114 dB, 192 kHz 8-Channel D/A Converter
Features
Description
 24-bit Conversion
 Up to 192 kHz Sample Rates
 114 dB Dynamic Range
 -100 dB THD+N
 Supports PCM and DSD Data Formats
 Selectable Digital Filters
 Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-Free Transitions
 Dedicated DSD Inputs
 Low Clock-Jitter Sensitivity
 Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
 μC or Stand-Alone Operation
The CS4382 is a complete 8-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-empha-
sis, volume control and analog filtering. The advantages
of this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4382 is available in a 48-pin LQFP package in
Commercial grade (-10°C to +70°C). The CDB4382
Customer Demonstration Board is also available for de-
vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 42 for com-
plete details.
The CS4382 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players,
SACD players, A/V receivers, digital TV’s, mixing con-
soles, effects processors, and automotive audio
systems.
I
D SD_SC LK(M 3)
S C L/C C LK (M 1) S D A /C D IN (M 2) A D 0/C S (M 0) V LC
MUTEC1
M U TEC234
RST
VLS
S C LK1
LRC K1
S CLK 2
L RCK2
SD I N1
SD I N2
SD I N3
SD I N4
M C LK
÷2
8
DSDxx
C ontrol P ort(S tand-A lone M ode S elect)
V olu m e C o ntro l
M ixer
V olu m e C o ntro l
V olu m e C o ntro l
M ixe r
V olu m e C o ntro l
V olu m e C o ntro l
M ixe r
V olu m e C o ntro l
V olu m e C o ntro l
M ixe r
V olu m e C o ntro l
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la ti o n F ilt e r
E xte rna l
M ute C o ntrol
ΔΣ D A C
A n a lo g F ilte r
ΔΣ D A C
ΔΣ D A C
A n a lo g F ilte r
A n a lo g F ilte r
ΔΣ D A C
ΔΣ D A C
A n a lo g F ilte r
A n a lo g F ilte r
ΔΣ D A C
ΔΣ D A C
A n a lo g F ilte r
A n a lo g F ilte r
ΔΣ D A C
A n a lo g F ilte r
VD
GND
GND
VA
A O U T A1+
A O U T A1-
A O U T B1+
A O U T B1-
A O U T A2+
A O U T A2-
A O U T B2+
A O U T B2-
A O U T A3+
A O U T A3-
A O U T B3+
A O U T B3-
A O U T A4+
A O U T A4-
A O U T B4+
A O U T B4-
VQ
F IL T +
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
FEB '08
DS514F2

1 page




CDB4382 pdf
1. CHARACTERISTICS AND SPECIFICATIONS
CS4382www.DataSheet4U.com
ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz; Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Test
load RL = 3 kΩ, CL = 100 pF, VA = 5 V, VD = 3.3 V (see Figure 5)
For Single-Speed Mode, Fs = 48 kHz, SCLK = 3.072 MHz, MCLK = 12.288 MHz;
For Double-Speed Mode, Fs = 96 kHz, SCLK = 6.144 MHz, MCLK = 12.288 MHz;
For Quad-Speed Mode, Fs = 192 kHz, SCLK = 12.288 MHz, MCLK = 24.576 MHz;
For Direct Stream Digital Mode, Fs = 128 x 48 kHz, DSD_SCLK = 6.144 MHz, MCLK = 12.288 MHz).
Parameters
Symbol Min
CS4382-KQZ Dynamic Performance - All PCM modes and DSD (Note 1)
Specified Temperature Range
Dynamic Range (Note 2)
24-bit unweighted
A-Weighted
16-bit unweighted
(Note 3) A-Weighted
TA
-10
105
108
-
-
Total Harmonic Distortion + Noise
24-bit
16-bit
(Note 3)
(Note 2)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
THD+N
-
-
-
-
-
-
Idle Channel Noise / Signal-to-noise ratio
-
Interchannel Isolation
(1 kHz)
-
Typ
-
111
114
94
97
-100
-91
-51
-94
-74
-34
114
90
Max Unit
70 °C
- dB
- dB
- dB
- dB
-94 dB
- dB
- dB
- dB
- dB
- dB
- dB
- dB
Notes:
1. CS4382-KQZ parts are tested at 25°C.
2. One-half LSB of triangular PDF dither is added to data.
3. Performance limited by 16-bit quantization noise.
DS514F2
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CDB4382 arduino
CS4382www.DataSheet4U.com
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® FORMAT
(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 19)
(Note 20)
Symbol
fscl
tirs
tbuf
thdst
tlow
thigh
tsust
thdd
tsud
trc, trc
tfc, tfc
tsusp
tack
Min
-
500
4.7
4.0
4.7
4.0
4.7
0
250
-
-
4.7
-
Max
100
-
-
-
-
-
-
-
-
1
300
-
(Note 21)
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
Notes:
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
21.
--------1---5----------
256 × Fs
for Single-Speed Mode,
--------1---5----------
128 × Fs
for Double-Speed Mode,
-------1---5--------
64 × Fs
for Quad-Speed Mode.
SDA
001100
ADDR
AD0
R/W ACK
Note 1
DATA
1-8
ACK
DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 3. Control Port Timing - I²C Format
DS514F2
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