PDF IDTCSPT855 Data sheet ( Hoja de datos )

Número de pieza	IDTCSPT855
Descripción	2.5V PHASE LOCKED LOOP CLOCK DRIVER
Fabricantes	Integrated Device Technology
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No Preview Available ! IDTCSPT855 2.5V PLL CLOCK DRIVER www.DataSheet4U.com COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.5V PHASE LOCKED LOOP CLOCK DRIVER IDTCSPT855 FEATURES: • PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications • Spread spectrum clock compatible • Operating frequency: 60MHz to 180MHz • Low jitter (cycle-to-cycle): ±50ps • Distributes one differential clock input to four differential clock outputs • Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low • Operates from dual 2.5V supplies • Consumes <200µA quiescent current • External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks • Available in TSSOP package DESCRIPTION: The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). WhenPWRDWN is high, the outputs switch in phase and frequencywithCLK. WhenPWRDWNislow,alloutputsaredisabledtoahigh- impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below asuggesteddetectionfrequencythatisbelow20MHz(typical10MHz). Aninput frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. The CSPT855 is also able to track spread spectrum clocking for reducted EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. FUNCTIONAL BLOCK DIAGRAM 24 PWRDWN AVDD 9 POWERDOWN AND TEST LOGIC CLK 6 CLK 7 FBIN 23 FBIN 22 PLL 3 Y0 2 Y0 12 Y1 13 Y1 17 Y2 16 Y2 26 Y3 27 Y3 19 FBOUT 20 FBOUT The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL c 2003 Integrated Device Technology, Inc. TEMPERATURE 1 RANGES APRIL 2003 DSC-6203/4 1 page IDTCSPT855 2.5V PLL CLOCK DRIVER www.DataSheet4U.com COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS Symbol Description tPLH(2) LOW to HIGH Level Propagation Delay Time tPHL(2) HIGH to LOW Level Propagation Delay Time tJIT(PER)(3) Jitter (period), see figure 6 tJIT(CC)(3) Jitter (cycle-to-cycle), see figure 2 tJIT(HPER)(3) Half-Period Jitter, see figure 7 tSLR(O) Output Clock Slew Rate (single-ended), see figure 8 tD(∅)(3) SSC Off Dynamic Phase Offset (includes jitter) see figure 4 SSC On t(∅) Static Phase Offset, see figure 3 tSK(O)(4) Output Skew, see figure 5 tR,tF Output Rise and Fall Times (20% to 80%) NOTES: 1. All typical values are at respective nominal VDDQ. 2. Refers to transition of non-inverting output. 3. This parameter guaranteed by design but not production tested. 4. All differential output pins are terminated with 120Ω / 14pF. Test Conditions Test mode, CLK to any output Test mode, CLK to any output 66MHz 100/ 133/ 167/ 180 MHz 66MHz 100/ 133/ 167/ 180 MHz 66MHz 100MHz 133/ 167/ 180 MHz Load: 120Ω / 14pF Load: 120Ω / 4pF 66MHz 100/ 133 MHz 167/ 180 MHz 66MHz 100/ 133 MHz 167/ 180 MHz 66MHz 100/ 133/ 167/ 180 MHz Load: 120Ω / 14pF Min. — — – 55 – 35 – 60 – 50 – 130 – 90 – 75 1 1 – 180 – 130 – 90 – 230 – 170 – 100 – 150 – 100 — 650 Typ.(1) 4.5 4.5 — — — — — — — — — — — — — — — — — — — Max. Unit — ns — ns 55 ps 35 60 ps 50 130 90 ps 75 2 V/ns 3 180 130 90 ps 230 170 100 150 ps 100 50 ps 900 ps 5 5 Page

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