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PDF ADP3206 Data sheet ( Hoja de datos )
| Número de pieza | ADP3206 | |
| Descripción | 2-/3-/4-Phase Synchronous Buck Controller | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP3206 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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2-/3-/4-Phase Synchronous Buck
Controller for IMVP-5 CPUswww.DataSheet4U.com
ADP3206
FEATURES
Selectable 2-, 3-, or 4-phase operation at up to
1 MHz per phase
6-bit digitally programmable 0.8375 V to 1.6 V output
±10 mV DAC accuracy over temperature
Logic-level PWM outputs for interface to
external high power drivers
Active current/thermal balancing between phases
Built-in power good/crowbar blanking supports
on-the-fly VID code changes
Programmable deep sleep offset and deeper sleep
reference voltage
Programmable soft transient control to minimize
inrush currents during output voltage changes
Programmable short circuit protection with
programmable latch-off delay
APPLICATIONS
Desk-note and notebook PC power supplies for IMVP-5
compliant Intel® processors
GENERAL DESCRIPTION
The ADP3206 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
the notebook main supply into the core supply voltage required
by IMVP-5 Intel processors. It uses an internal 6-bit DAC to
read a voltage identification (VID) code directly from the
processor, which is used to set the output voltage between
0.8375 V and 1.6 V, and uses a multimode PWM architecture
to drive the logic-level outputs at a programmable switching
frequency that can be optimized for VR size and efficiency. The
phase relationship of the output signals can be programmed to
provide 2-, 3-, or 4-phase operation.
The ADP3206 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3206 also provides accurate and reliable
short circuit protection, adjustable current limiting, deep sleep
and deeper sleep programming inputs, and a delayed power
good output that accommodates on-the-fly output voltage
changes requested by the CPU.
ADP3206 is specified over the commercial temperature range of
0°C to 100°C and is available in a 40-lead LFCSP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
35
RAMPADJ RT
16 15
SD 13
UVLO
SHUTDOWN
AND BIAS
OSCILLATOR
GND 21
TTMASK 22
TTSENSE 23
VRTT 24
ADP3206
THERMAL
THROTTLING
CONTROL
CURRENT-
BALANCING
CIRCUIT
CSREF
CMP
SET EN
RESET
34 PWM1
CMP
CMP
RESET
33 PWM2
2-/3-/4-PHASE
DRIVER LOGIC
RESET
32 PWM3
CMP RESET
CROWBAR
31 PWM4
PWRGD 12
DELAY 14
ILIMIT 17
COMP 4
DELAY
SOFT
START
PRECISION
REFERENCE
CURRENT LIMIT
CURRENT-
LIMITING
CIRCUIT
28 SW1
27 SW2
26 SW3
25 SW4
19 CSSUM
18 CSREF
20 CSCOMP
VID
DAC
DEEP/
DEEPER
SLEEP
CONTROL
3 FB
11 DPSLP
10 DPSET
9 DPRSLP
8 DPRSET
5 PGMASK
29 OD2
30 OD1
6 STSET
2 7 40 39 38 37 36 1
FBRTN REF VID0 VID1 VID2 VID3 VID4 VID5
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
SHUTDOWN INPUT
Input Low Voltage
Input High Voltage
Input Current, Input Voltage Low
Input Current, Input Voltage High
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
VID Code Changing
VID Code Static
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
POWER GOOD MASKING
Threshold Voltage
Output Current
Symbol
VIL(SD)
VIH(SD)
IIL(SD)
IIH(SD)
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
VCROWBAR
tCROWBAR
PWM OUTPUTS
Output Voltage Low
Output Voltage High
SUPPLY
Supply Voltage Range
Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
VOL(PWM)
VOH(PWM)
VCC
ICC
VUVLO
∆VUVLO
Conditions
SD = 0 V
SD = 1.25 V
Relative to nominal output
Relative to nominal output
IPWRGD(SINK) = 4 mA
CPGMASK = 150 pF
Relative to nominal output
Overvoltage to PWM going low
CPGMASK = 150 pF
DPRSLP or VID changing,
VPGMASK = 0 V
DPRSLP or VID static,
VPGMASK = 0.5 V
IPWM(SINK) = 400 µA
IPWM(SOURCE) = 400 µA
VCC Rising
ADP3206
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Min Typ
Max Unit
0.8
−1
10
0.4 V
V
1 µA
25 µA
−200
100
−250
150
150
−300
200
400
mV
mV
mV
90 µs
200 ns
100 150 200 mV
350 450 550 mV
90 µs
400 ns
2.85 3
3.5 5
3.15 V
6.5 µA
500 µA
100 500 mV
4.0 5.0
V
4.5 5.5 V
3.5 6
mA
3.6 3.8 4.1 V
50 100 150 mV
1 All limits at temperature extremes are guaranteed via correlation using Standard Statistical Quality Control (SQC).
2 Guaranteed by design or bench characterization, not production tested.
Rev. 0| Page 5 of 32
5 Page 
THEORY OF OPERATION
The ADP3206 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel's IMVP-5
specifications. Multiphase operation is important for producing
the high currents and low voltages demanded by today's
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.
The multimode control of the ADP3206 ensures a stable, high
performance topology for
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
• Tight load line regulation and accuracy
• High current output from having up to 4 phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation for tailoring design to low cost or
high performance
NUMBER OF PHASES
The number of operational phases and their phase relationship
is determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3206 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase
operation, and grounding the PWM3 and PWM4 pins
programs 2-phase operation.
When the ADP3206 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550 mV. An
internal comparator checks each pin's voltage versus a threshold
of 300 mV. If the pin is grounded, then it is below the threshold
and the phase is disabled. The output impedance of the PWM
pin is approximately 5 kΩ during the phase detect. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper phase detection. The phase
detection is made during the first two clock cycles of the
internal oscillator. After this time, if the PWM output was not
grounded, then it switches between 0 V and 5 V. If the PWM
output was grounded, then switching to the pin remains off.
ADP3206
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The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3419. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3206 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is to be divided by the number of phases in use.
If PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are
grounded, then divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3206 combines differential sensing with a high
accuracy VID DAC, precision REF output, and a low offset error
amplifier to meet Intel's IMVP-5 specification. During normal
mode, the VID DAC and error amplifier maintain a worst-case
specification of ±10 mV over the full operating output voltage
and temperature range. For Deeper Sleep operation, an external
resistor divider from the REF pin to FBRTN creates the
DPRSET voltage. This voltage is buffered by a low offset, slew
rate limited amplifier that is used to drive the noninverting
input of the error amplifier.
The core output voltage is sensed between the FB and FBRTN
pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the
microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC, DPRSET
voltage, and precision REF output are referenced to FBRTN,
which has a minimal current of 100 µA to allow accurate
remote sensing.
OUTPUT CURRENT SENSING
The ADP3206 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method then peak current detection or sampling the
current across a sense element such as the low side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system:
• Output inductor ESR sensing without thermistor for
lowest cost
• Output inductor ESR sensing with thermistor to
improve accuracy for tracking inductor temperature
• Sense resistors for highest accuracy measurements
Rev. 0| Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP3206.PDF ] | |
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