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PDF DAC1405D750 Data sheet ( Hoja de datos )
| Número de pieza | DAC1405D750 | |
| Descripción | Dual 14-bit DAC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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DAC1405D750
www.DataSheet4U.com
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Rev. 01 — 10 March 2010
Preliminary data sheet
1. General description
The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 4× or 8× interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q
inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
A 4× and 8× clock multiplier enables the DAC1405D750 to provide the appropriate
internal clocks from the internal PLL. The internal PLL can be bypassed enabling the use
of an external high frequency clock. The voltage regulator enables adjustment of the
output full-scale current.
2. Features and benefits
Dual 14-bit resolution
IMD3: 76 dBc; fs = 737.28 Msps;
750 Msps maximum update rate
fo = 140 MHz
ACPR: 71 dBc; 2-carrier WCDMA;
fs = 737.28 Msps; fo = 153.6 MHz
Selectable 4× or 8× interpolation filters Typical 1.2 W power dissipation at 4×
interpolation, PLL off and 740 Msps
Input data rate up to 185 Msps
Power-down and Sleep modes
Very low noise cap-free integrated PLL Differential scalable output current from
1.6 mA to 22 mA
32-bit programmable NCO frequency On-chip 1.25 V reference
Dual port or Interleaved data modes External analog offset control
(10-bit auxiliary DACs)
1.8 V and 3.3 V power supplies
Internal digital offset control
LVDS compatible clock
Inverse x / (sin x) function
Two’s complement or binary offset Fully compatible SPI port
data format
1.8 V/3.3 V CMOS input buffers
Industrial temperature range from
−40 °C to +85 °C
1 page  
NXP Semiconductors
DAC1405D750
www.DataSheet4U.com
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
6.2 Pin description
Table 2. Pin description
Symbol
Pin Type[1]
VDDA(3V3)
AUXAP
1
2
P
O
AUXAN 3 O
AGND
4G
VDDA(1V8)
VDDA(1V8)
AGND
5
6
7
P
P
G
CLKP
8I
CLKN
9I
AGND
10 G
VDDA(1V8)
SYNCP
11
12
P
O
SYNCN
13 O
TM1 14 I/O
TM0 15 I/O
VDD(IO)(3V3)
GNDIO
16
17
P
G
I13 18 I
I12 19 I
I11 20 I
I10 21 I
I9 22 I
I8 23 I
I7 24 I
I6 25 I
VDDD(1V8)
DGND
26
27
P
G
I5 28 I
I4 29 I
I3 30 I
I2 31 I
VDDD(1V8)
DGND
32
33
P
G
I1 34 I
I0 35 I
VDDD(1V8)
DGND
36
37
P
G
TM2 38 -
DGND
39 G
Description
analog supply voltage 3.3 V
auxiliary DAC B output current
complementary auxiliary DAC B output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
clock input
complementary clock input
analog ground
analog supply voltage 1.8 V
synchronous clock output
complementary synchronous clock output
test mode 1 (connected to DGND)
test mode 0 (connected to DGND)
input/output buffers supply voltage 3.3 V
input/output buffers ground
I data input bit 13 (MSB)
I data input bit 12
I data input bit 11
I data input bit 10
I data input bit 9
I data input bit 8
I data input bit 7
I data input bit 6
digital supply voltage 1.8 V
digital ground
I data input bit 5
I data input bit 4
I data input bit 3
I data input bit 2
digital supply voltage 1.8 V
digital ground
I data input bit 1
I data input bit 0 (LSB)
digital supply voltage 1.8 V
digital ground
test mode 2 (to connect to DGND)
digital ground
DAC1405D750_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 March 2010
© NXP B.V. 2010. All rights reserved.
5 of 43
5 Page 
NXP Semiconductors
DAC1405D750
www.DataSheet4U.com
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
Table 5. Characteristics …continued
VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together;
Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω differential; IO(fs) = 20 mA; PLL off unless
otherwise specified.
Symbol
Parameter
Conditions
Test[1] Min Typ
Max
Unit
Input timing (see Figure 10)
fdata
tw(CLK)
th(i)
tsu(i)
SYNC signal
data rate
CLK pulse width
input hold time
input set-up time
Dual-port mode input
C
C
C
C
-
40
<tbd>
<tbd>
-
-
-
-
185 MHz
60 %
- ns
- ns
td delay time
fSYNC = fs / 4
fSYNC = fs / 8
variation
C - 0.21 -
C - 0.3 -
C - 0.27 -
ns
ns
ps/°C
Output timing
fs sampling frequency
ts settling time
NCO frequency range
to ± 0.5 LSB
C --
750 Msps
D
- 20
-
ns
fNCO
NCO frequency
register values
0000 0000h
D -0 -
MHz
FFFF FFFFh
D
- 740 -
MHz
fstep step frequency
Low-power NCO frequency range
D
-
0.172
-
Hz
fNCO
NCO frequency
register values
0000 0000h
D -0 -
MHz
F800 0000h
D - 716.875 -
MHz
fstep step frequency
Dynamic performance
D - 23.125 -
MHz
SFDR
spurious-free dynamic
range
SFDRRBW
restricted bandwidth
spurious-free dynamic
range
fs = 737.28 Msps
fdata = 91.6 MHz; B = fdata / 2
fo = 4 MHz; 0 dBFS
C
fdata = 184.32 MHz; B = fdata / 2
fo = 19 MHz; 0 dBFS I
fo = 70 MHz; 0 dBFS C
-
-
-
76
74
86
-
-
-
fo = 153.6 MHz; 0 dBFS; fdata = 184.32 MHz; fs = 737.28 Msps
B = 20 MHz
C
- 85
-
dBc
dBc
dBc
dBc
B = 100 MHz
C
- 83
-
dBc
B = 20 MHz; 8-tone; C
500 kHz spacing
- 75
-
dBc
DAC1405D750_1
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 March 2010
© NXP B.V. 2010. All rights reserved.
11 of 43
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