PDF DAC1405D650 Data sheet ( Hoja de datos )

Número de pieza	DAC1405D650
Descripción	Dual 14-bit DAC
Fabricantes	NXP Semiconductors
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No Preview Available ! DAC1405D650 www.DataSheet4U.com Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating Rev. 01 — 4 May 2009 Product data sheet 1. General description The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating ﬁlters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register. Two modes of operation are available: separate data ports or a single interleaved high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into its original I and Q data and then latched. The DAC1405D650 also includes a 2×, 4× and 8× clock multiplier which provides the appropriate internal clocks and an internal regulator to adjust the output full-scale current. 2. Features I Dual 14-bit resolution I 650 Msps maximum update rate I IMD3: 80 dBc; fs = 640 Msps; fo = 96 MHz I ACPR: 71 dBc; 2 carriers WCDMA; fs = 614.4 Msps; fo = 96 MHz; PLL on I Selectable 2×, 4× or 8× interpolation I Typical 0.95 W power dissipation at 4× ﬁlters interpolation I Input data rate up to 160 Msps I Power-down and Sleep modes I Very low noise cap-free integrated PLL I Differential scalable output current from 1.6 mA to 22 mA I 32-bit programmable NCO frequency I On-chip 1.25 V reference I Dual port or Interleaved data modes I External analog offset control (10-bit auxiliary DACs) I 1.8 V and 3.3 V power supplies I Internal digital offset control I LVDS compatible clock I Inverse (sin x) / x function I Two’s complement or binary offset I Fully compatible SPI port data format I 3.3 V CMOS input buffers I Industrial temperature range from −40 °C to +85 °C 1 page NXP Semiconductors DAC1405D650 www.DataSheet4U.com Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating 6.2 Pin description Table 2. Pin description Symbol Pin Type[1] VDDA(3V3) AUXAP 1 2 P O AUXAN 3 O AGND 4G VDDA(1V8) VDDA(1V8) AGND 5 6 7 P P G CLKP 8I CLKN 9I AGND 10 G VDDA(1V8) 11 P d.n.c. 12 - d.n.c. 13 - TM1 14 I/O TM0 15 I/O VDD(IO)(3V3) GNDIO 16 17 P G I13 18 I I12 19 I I11 20 I I10 21 I I9 22 I I8 23 I I7 24 I I6 25 I VDDD(1V8) DGND 26 27 P G I5 28 I I4 29 I I3 30 I I2 31 I VDDD(1V8) DGND 32 33 P G I1 34 I I0 35 I VDDD(1V8) DGND 36 37 P G TM2 38 - DGND 39 G Description analog supply voltage 3.3 V auxiliary DAC B output current complementary auxiliary DAC B output current analog ground analog supply voltage 1.8 V analog supply voltage 1.8 V analog ground clock input complementary clock input analog ground analog supply voltage 1.8 V do not connect do not connect test mode 1 (to connect to DGND) test mode 0 (to connect to DGND) input/output buffers supply voltage 3.3 V input/output buffers ground I data input bit 13 (MSB) I data input bit 12 I data input bit 11 I data input bit 10 I data input bit 9 I data input bit 8 I data input bit 7 I data input bit 6 digital supply voltage 1.8 V digital ground I data input bit 5 I data input bit 4 I data input bit 3 I data input bit 2 digital supply voltage 1.8 V digital ground I data input bit 1 I data input bit 0 (LSB) digital supply voltage 1.8 V digital ground test mode 2 (to connect to DGND) digital ground DAC1405D650_1 Product data sheet Rev. 01 — 4 May 2009 © NXP B.V. 2009. All rights reserved. 5 of 43 5 Page NXP Semiconductors DAC1405D650 www.DataSheet4U.com Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = −40 °C to +85 °C; typical values measured at Tamb = 25 °C; RL = 50 Ω; IO(fs) = 20 mA; maximum sample rate; PLL on unless otherwise speciﬁed. Symbol Parameter Conditions Test Min Typ Max [1] Unit Analog auxiliary outputs (AUXAP, AUXAN, AUXBP and AUXBN) IO(aux) VO(aux) NDAC(aux)mono auxiliary output current auxiliary output voltage auxiliary DAC monotonicity differential outputs compliance range guaranteed I- C0 D- Input timing (see Figure 10) fdata data rate tw(CLK) CLK pulse width th(i) input hold time tsu(i) input set-up time Output timing Dual-port mode input C- C 1.5 C 1.1 C 1.1 fs sampling frequency ts settling time to ±0.5 LSB NCO frequency range; fs = 640 Msps fNCO NCO frequency register value = 00000000h register value = FFFFFFFFh C D D D - - - - fstep step frequency Low-power NCO frequency range; fDAC = 640 MHz fNCO NCO frequency register value = 00000000h register value = F8000000h D D D - - - fstep step frequency Dynamic performance; PLL on D- SFDR SFDRRBW spurious-free dynamic range restricted bandwidth spurious-free dynamic range fdata = 80 MHz; fs = 320 Msps; BW = fdata / 2 fo = 35 MHz at 0 dBFS C- fdata = 80 MHz; fs = 640 Msps; BW = fdata / 2 fo = 4 MHz at 0 dBFS I- fo = 19 MHz at 0 dBFS I- fdata = 160 MHz; fs = 640 Msps; BW = fdata / 2 fo = 70 MHz at 0 dBFS C- fs = 640 Msps; fo = 96 MHz at 0 dBFS 2.51 MHz ≤ foffset ≤ 2.71 MHz; I B = 30 kHz - 2.71 MHz ≤ foffset ≤ 3.51 MHz; I B = 30 kHz [4] - 3.51 MHz ≤ foffset ≤ 4 MHz; B = 30 kHz I 4 MHz ≤ foffset ≤ 40 MHz; B = 1 MHz I - 2.2 - -2 10 - mA V bit - 160 MHz - Tdata − 1.5 ns -- ns -- ns - 650 20 - Msps ns 0- 640 - 0.149 - MHz MHz Hz 0- 620 - 20 - MHz MHz MHz 84 - 77 - 76 - 84 - −93 −86 −92 - −93 −88 −85 −72 dBc dBc dBc dBc dBc dBc dBc dBc DAC1405D650_1 Product data sheet Rev. 01 — 4 May 2009 © NXP B.V. 2009. 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