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PDF LH28F016SCT-ZR Data sheet ( Hoja de datos )
| Número de pieza | LH28F016SCT-ZR | |
| Descripción | Flash Memory 16Mbit (2Mbitx8) | |
| Fabricantes | Sharp Microelectronics | |
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PRODUCT SPECIFICATION
Integrated Circwuwiwts.DaGtarSoheuept4U.com
LH28F016SCT-ZR
Flash Memory
16Mbit (2Mbitx8)
(Model Number: LHF16CZR)
Spec. Issue Date: October 14, 2004
Spec No: EL16X101
1 page  
LHF16CZR
2
LH28F016SCT-ZR
16M-BIT (2 MB x 8)
SmartVoltage Flash MEMORY
www.DataSheet4U.com
■ SmartVoltage Technology
2.7V(Read-Only), 3.3V or 5V VCC
3.3V, 5V or 12V VPP
■ High-Performance Read Access Time
90ns(5V±0.25V), 100ns(5V±0.5V),
120ns(3.3V±0.3V), 150ns(2.7V-3.6V)
■ Operating Temperature
0°C to +70°C
■ High-Density Symmetrically-Blocked
Architecture
Thirty-two 64K-byte Erasable Blocks
■ Extended Cycling Capability
100,000 Block Erase Cycles
3.2 Million Block Erase Cycles/Chip
■ Industry-Standard Packaging
40-Lead TSOP
■ Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
■ Automated Byte Write and Block Erase
Command User Interface
Status Register
■ Enhanced Automated Suspend Options
Byte Write Suspend to Read
Block Erase Suspend to Byte Write
Block Erase Suspend to Read
■ Enhanced Data Protection Features
Absolute Protection with VPP=GND
Flexible Block Locking
Block Erase/Byte Write Lockout
during Power Transitions
■ SRAM-Compatible Write Interface
■ ETOXTM* Nonvolatile Flash Technology
■ CMOS Process
(P-type silicon substrate)
■ Not designed or rated as radiation
hardened
SHARP’s LH28F016SCT-ZR Flash memory with SmartVoltage technology is a high-density, low-cost, nonvolatile,
read/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SIMMs and memory
cards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F016SCT-ZR offers three levels of protection: absolute protection with VPP at
GND, selective hardware block locking, or flexible software block locking. These alternatives give designers
ultimate control of their code security needs.
The LH28F016SCT-ZR is manufactured on SHARP’s 0.38µm ETOXTM process technology. It come in
industry-standard package: the 40-lead TSOP, ideal for board constrained applications. Based on the 28F008SA
architecture, the LH28F016SCT-ZR enables quick and easy upgrades for designs demanding the state-of-the-art.
*ETOX is a trademark of Intel Corporation.
Rev. 1.2
5 Page 
LHF16CZR
8
2.1 Data Protection
Depending on the application, the system designer
may choose to make the VPP power supply
switchable (available only when memory block
erases, byte writes, or lock-bit configurations are
required) or hardwired to VPPH1/2/3. The device
accommodates either design practice and
encourages optimization of the processor-memory
interface.
When VPP≤VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase, byte
write, or lock-bit configuration command sequences,
provides protection from unwanted operations even
when high voltage is applied to VPP. All write
functions are disabled when VCC is below the write
lockout voltage VLKO or when RP# is at VIL. The
device’s block locking capability provides additional
protection from inadvertent code or data alteration by
gating erase and byte write operations.
3 BUS OPERATION
The local CPU reads and writes flash memory
in-system. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, or status register independent of the VPP
voltage. RP# can be at either VIH or VHH.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from deep power-down mode,
the device automatically resets to read array mode.
Four control pins dictate the data flow in and out of
the component: CE#, OE#, WE#, and RP#. CE# and
OE# must be driven active to obtain data at the
outputs. CE# is the device selection control, and
when active enables the selected memory device.
OE# is the data output (DQ0-DQ7) control and when
active drives the selected memory data onto the I/O
bus. WE# must be at VIH and RP# must be at VIH or
VHH. Figure 15 illustrates a read cycle.
3.2 Output Disable
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With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins DQ0-DQ7 are
placed in a high-impedance state.
3.3 Standby
CE# at a logic-high level (VIH) places the device in
standby mode which substantially reduces device
power consumption. DQ0-DQ7 outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, byte write, or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation
completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read modes, RP#-low deselects the memory,
places output drivers in a high-impedance state and
turns off all internal circuits. RP# must be held low for
a minimum of 100 ns. Time tPHQV is required after
return from power-down until initial memory access
outputs are valid. After this wake-up interval, normal
operation is restored. The CUI is reset to read array
mode and status register is set to 80H.
During block erase, byte write, or lock-bit
configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset
operation is complete. Memory contents being
altered are no longer valid; the data may be partially
erased or written. Time tPHWL is required after RP#
goes to logic-high (VIH) before another command can
be written.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, byte
write, or lock-bit configuration modes. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash memory
may be providing status information instead of array
data. SHARP’s flash memories allow proper CPU
initialization following a system reset through the use
of the RP# input. In this application, RP# is controlled
by the same RESET# signal that resets the system
CPU.
Rev. 1.2
11 Page | ||
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