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Numéro de référence | M30W0R6500T0 | ||
Description | Multi-Chip Package | ||
Fabricant | ST Microelectronics | ||
Logo | |||
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M30W0R6500T0
96 Mbit (64 + 32Mb, x16, Multiple Bank, Burst, Flash Memories)
1.8V Supply, Multi-Chip Package
FEATURES SUMMARY
■ MULTI-CHIP PACKAGE
– 1 die of 64 Mbit (4Mb x 16) Flash Memory
– 1 die of 32 Mbit (2Mb x 16) Flash Memory
■ SUPPLY VOLTAGE
– VDDF1 = VDDF2 = VDDQ = 1.7 to 2.2V
– VPP = 12V for fast Program (optional)
■ LOW POWER CONSUMPTION
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– 64Mb Device Code (Top Configuration):
8810h
– 32Mb Device Code (Top Configuration):
8814h
■ PACKAGE
– Compliant with Lead-Free Soldering
Processes
– Lead-Free Versions
FLASH MEMORY
■ SYNCHRONOUS / ASYNCHRONOUS READ
– Synchronous Burst Read mode: 54MHz
– Asynchronous/ Synchronous Page Read
mode
– Random Access: 70ns
■ PROGRAMMING TIME
– 8µs by Word typical for Fast Factory
Program
– Double/Quadruple Word Program option
– Enhanced Factory Program options
■ ARCHITECTURE
– 64Mbit and 32Mbit Flash memories
– Multiple Bank Memory Array: 4 Mbit
Banks
– Parameter Blocks (Top location)
■ DUAL OPERATIONS
– Program Erase in one Bank while Read in
others
– No delay between Read and Write
operations
Figure 1. Packages
FBGA
Stacked LFBGA88 (ZA)
8 x 10mm
■ BLOCK LOCKING
– All blocks locked at Power up
– Any combination of blocks can be locked
– WP for Block Lock-Down
■ SECURITY
– 128 bit user programmable OTP cells
– 64 bit unique device number
– One parameter block permanently
lockable
■ COMMON FLASH INTERFACE (CFI)
■ 100,000 PROGRAM/ERASE CYCLES per
BLOCK
December 2004
1/19
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Pages | Pages 19 | ||
Télécharger | [ M30W0R6500T0 ] |
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