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Toshiba America Electronic - 512-megabit XDRTM DRAM The Rambus XDRTM DRAM device

Numéro de référence TC59YM916BKG40C
Description 512-megabit XDRTM DRAM The Rambus XDRTM DRAM device
Fabricant Toshiba America Electronic 
Logo Toshiba America Electronic 





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TC59YM916BKG40C fiche technique
TC59YM916BKG24A,32A,32B,40B,32C,40C
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT
OVERVIEW
SILICON MONOLITHIC
Lwewawd.DaFtareSheeet4U.com
The Rambus XDRTM DRAM device is a general purpose high-performance memory device suitable for use in a
broad range of applications including computer memory, graphics, video, and any other application where high
bandwidth and low latency are required.
The 512Mb Rambus XDR DRAM device is a CMOS DRAM organized as 32M words by 16 bits. The use of
Differential Rambus Signaling Level (DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using
conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of
8000/6400/4800 MB/s.
XDR DRAM device architecture allows the highest sustained bandwidth for multiple, interleaved randomly
addressed memory transactions. The highly efficient protocol yields over 95% utilization while allowing fine access
granularity. The device's 8 banks support up to four interleaved transactions.
FEATURES
Highest pin bandwidth available
4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
Bi-directional differential RSL (DRSL)
Flexible read/write bandwidth allocation
Minimum pin count
Programmable on-chip termination
Adaptive impedance matching
Reduced system cost and routing complexity
Highest sustained bandwidth per DRAM device
8000/6400/4800 MB/s sustained data rate
8 banks: bank-interleaved transactions at full bandwidth
Dynamic request scheduling
Early-Read-after-Write support for maximum efficiency
Zero overhead refresh
Low latency
2.0/2.5/3.33 ns request packets
Point-to-point data interconnect for fastest possible flight time
Support for low-latency, fast-cycle cores
Low power
1.8V VDD
Programmable small-swing I/O signaling (DRSL)
Low power PLL/DLL design
Power Down Self Refresh support
Per pin I/O Power Down for narrow-width operation
Programmable I/O width
− ×4 / ×8 / ×16 programmable device I/O width
Lead Free
Note: XDR is a trademark or a registered trademark in Japan and/or other countries.
Rev 0.1
2004-12-15 1/76

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