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PDF NJW1183 Data sheet ( Hoja de datos )
| Número de pieza | NJW1183 | |
| Descripción | Audio Processor | |
| Fabricantes | SRS Labs | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJW1183 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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NJW1183
www.DataSheet4U.com
Audio Processor with SRS WOW
s GENERAL DESCRIPTION
The NJW1183 is an audio processor with SRS WOW. It includes
all of functions processing audio signal for TV, such as volume,
balance and tone control. All of internal status and variables are
controlled by I2C BUS.
s PACKAGE OUTLINE
s FEATURES
q Operating Voltage
8 to 13 V
q SRS WOW (including SRS 3D, FOCUS and TruBass function)
q Simulated Stereo
q 4ch Input Selector
q Volume
0 to -80dB (0.5dB/step), MUTE
q Balance
0 to -30dB (1dB/step), MUTE
q Tone Control
-9dB to +9dB(1dB/step)
q I2C BUS Interface
q Bi-CMOS Technology
q Package Outline
SDIP42
NJW1183L
s BLOCK DIAGRAM
CVO
VOL2
CBA
INa
VOL1
Tone
CTH
Logic
CTL
AGC
WOW/Simulated
(FOCUS/TruBass/SRS 3D)
VOL2
CSR
CTB
CFCS
INb
VOL1
Tone
VOL2
V+
Bias
GND
–1–
1 page  
NJW1183
www.DataShee
s I2C BUS CHARACTERISTICS (SDA, SCL)
I2C BUS Load Conditions: Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
PARAMETER
STANDARD MODE
FAST MODE
SYMBOL
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
Low Level Input Voltage
VIL 0.0 - 1.5 0.0 - 1.5 V
High Level Input Voltage
VIH 2.7 - 5.0 2.7 - 5.0 V
Hysteresis of Schmitt trigger inputs
Vhys - - - 0.25 - - V
LOW level output voltage (3mA at SDA pin)
VOL 0 - 0.4 0 - 0.4 V
Output fall time from VIHmin to VILmax with
a bus capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed by the
input filter
tof
tSP
-
- 250 20
- 250 ns
+0.1Cb
- - - 0 - 50 ns
Input current each I/O pin with an input voltage
between 0.1VDD and 0.9VDDmax
Ii
-10 -
10 -10 -
10 µA
Capacitance for each I/O pin
Ci - - 10 - - 10 pF
SCL clock frequency
fSCL - - 100 - - 400 kHz
Hold time (repeated) START condition.
tHD:STA 4.0 -
- 0.6 -
- µs
LOW period of the SCL clock
tLOW 4.7 - - 1.3 - - µs
HIGH period of the SCL clock
tHIGH
4.0 -
- 0.6 -
- µs
Set-up time for a repeated START condition
tSU:STA 4.7 -
- 0.6 -
- µs
Data hold time
tHD:DAT 0 - 3.45 0 - 0.9 µs
Data set-up time
tSU:DAT
250
-
- 100 -
- ns
Rise time of both SDA and SCL signals
tr - - 1000 - - 300 ns
Fall time of both SDA and SCL signals
tf - - 300 - - 300 ns
Set-up time for STOP condition
tSU:STO 4.0 -
Bus free time between a STOP and START
condition
tBUF
4.7 -
- 0.6 -
- 1.3 -
- µs
- µs
Capacitive load for each bus line
Cb - - 400 - - 400 pF
Noise margin at the LOW level
VnL 0.5 - - 0.5 - - V
Noise margin at the HIGH level
VnH 1 - - 1 - - V
Cb ; total capacitance of one bus line in pF.
SDA
tf
tr
SCL
tHD:STA
S
tLOW
tSU:DAT
tf
tHD:STA
tHD:DAT
tHIGH
tSU:STA
Sr
tSP tr
tBUF
tSU:STO
P
S
–5–
5 Page 
s Master Volume (Select Address: 00H)
Gain(dB)
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
-29
-30
-31
-32
-33
-34
-35
-36
-37
-38
-39
-40
-41
-42
HEX
FF
FD
FB
F9
F7
F5
F3
F1
EF
ED
EB
E9
E7
E5
E3
E1
DF
DD
DB
D9
D7
D5
D3
D1
CF
CD
CB
C9
C7
C5
C3
C1
BF
BD
BB
B9
B7
B5
B3
B1
AF
AD
AB
D7
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
D6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
D5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VOL
D4 D3
11
11
11
11
10
10
10
10
01
01
01
01
00
00
00
00
11
11
11
11
10
10
10
10
01
01
01
01
00
00
00
00
11
11
11
11
10
10
10
10
01
01
01
NJW1183
www.DataSheet4U.com
D2 D1 D0
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
001
111
101
011
– 11 –
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet NJW1183.PDF ] | |
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