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PDF SEN6A40 Data sheet ( Hoja de datos )
| Número de pieza | SEN6A40 | |
| Descripción | 68-ROW driver | |
| Fabricantes | Avant Electronics | |
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DATA SHEET
www.DataSheet4U.com
SEN6A40
68-ROW driver for
dot-matrix STN LCD
To improve design and/or performance,
Avant Electronics may make changes to its
products. Please contact Avant Electronics
for the latest versions of its products
data sheet (v3)
2005 Oct 20
1 page  
Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
3.2 Signal description
Table 2 Pin signal description.
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To avoid a latch-up effect at power-on: VSS − 0.5 V < voltage at any pin at any time < VDD + 0.5 V .
Pin
number
SYMBOL
I/O
DESCRIPTION
1,
25~36,
40~61,
65~86,
90~100
O68,
O1~O12,
O13~O34,
O35~O56,
O57~O67
2, 19 DIO2, DIO1
3
4
5, 6, 10,
12, 14,
16,
20~24,
37~39,
62~64,
87~89
LP
FR
NC
COMMON driver output.
Output Please refer to Fig. 2 for pin assignment and Table 4 for output voltage level.
Input/output for COMMON scan data. COMMON scan data is sent out by the
I/O controller SAP1024B from its CDATA output. The COMMON scan data is for
horizontal scan line synchronization.
I Horizontal line pule, used as shift clock of the internal 68-bit shift register.
I Frame signal. This signal is used to generate alternating LCD bias voltage.
No Connection.
These pins should be left open in application.
Terminal switch.
7 TSW
I When this pin is connected to VDD, O1~O68 are output on the falling edge of LP.
8
9
11
13
15, 17,
18
VSS
DUAL
DIR
VDD
V4, V1, V5
I
Input
When this pin is connected to VSS, O1~O68 are output on the rising edge of LP.
Ground.
Select dual input mode or single input mode. Please refer to Table 5.
Select the shift direction of the scan data. Please refer to Table 5.
Power supply for control logic.
LCD bias voltage.
2005 Oct 20
5 of 20
data sheet (v3)
5 Page 
Avant Electronics
SEN6A40
68-ROW driver for dot-matrix STN LCD
7 DC CHARACTERISTICS
Table 7 DC Characteristics
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VDD = 5V ±10%; VSS = 0 V; all voltages with respect to VSS unless otherwise specified; Tamb = 25±2 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
VDD
Supply voltage for control logic
Please refer to Fig. 10 for
DC power-up sequence.
2.7
5.0
5.5 V
VDD-V5 LCD bias voltage
Note 1.
12 30
VIL
Input LOW voltage of input pins
DIO1, DIO2, LP, TSW, FR,
DUAL, DIR
0
0.2 VDD V
VIH
Input HIGH voltage of input pins
DIO1, DIO2, LP, TSW, FR,
DUAL, DIR
0.8 VDD
VDD
V
VOL
Output LOW voltage level of the
DIO1 and DIO2 pins
IOL=400µA
0.0 0.4 V
VOH
Output HIGH voltage level of the
DIO1 and DIO2 pins
IOH=-400µA
VDD − 0.4
VDD
V
ISTBY
Standby current
Note 2.
2 µA
ISS
IEE
RON1
RON2
Operating current
Operating current
Driver ON resistance at
VLCD= 30 V
Driver ON resistance at
VLCD= 20 V
Note 3.
Note 4.
Note 5.
Note 6.
80 µA
80 µA
1.0 ΚΩ
1.0 ΚΩ
Notes:
1. The following coditions: VDD ≥ V1 > V4 > V5 must always be met.
2. VDD-V5=30 V, LP=LOW, Output unloaded; measured at the VSS pin.
3. Condition for the measurement: VLCD=VDD-V5=30 V, VDD=5.5 V, LP=14 KHz, No load. This is the current flowing
from VDD to VSS, measured at the VSS pin.
4. Condition for the measurement: VLCD=VDD-V5=30 V, VDD=5.5 V, LP=14 KHz, No load. This is the current flowing
from VDD to V5, measured at the V5 pin.
5. Condition for the measurment: VDD-V5=30 V, |VDE-VO|=0.5 V, where VDE= one of V1, V4, or V5.
V1=VDD - (1/9) x (VDD-V5), V4=VDD - (8/9) x (VDD-V5). For the driver circuits (O1~O68), please refer to Section 12,
Pin Circuits.
6. Condition for the measurment: VDD-V5=20 V, |VDE-VO|=0.5 V, where VDE= one of V1, V4, or V5.
V1=VDD - (1/9) x (VDD-V5), V4=VDD - (8/9) x (VDD-V5). For the driver circuits (O1~O68), please refer to Section 12,
Pin Circuits.
2005 Oct 20
11 of 20
data sheet (v3)
11 Page | ||
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