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PDF HYB18T256161AF-28 Data sheet ( Hoja de datos )
| Número de pieza | HYB18T256161AF-28 | |
| Descripción | 256-Mbit x16 GDDR2 DRAM | |
| Fabricantes | Infineon | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HYB18T256161AF-28 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Data Sheet, Rev. 1.30, July 2005
www.DataSheet4U.com
HYB18T256161AF–22/25/28/33
HYB18T256161AFL25/28/33
256-Mbit x16 GDDR2 DRAM
RoHS compliant
Memory Products
Never stop thinking.
1 page  
HYB18T256161AF–[22/25/28/33] L[25/28/33]
256-Mbit DDR2 SGRAM
www.DataSheet4U.com
5.3
5.4
5.4.1
5.5
5.6
5.7
6
6.1
6.2
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
9
9.1
9.2
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Default Output V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Calibrated Output Driver V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Power & Ground Clamp V-I Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
IDD Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Electrical Characteristics & AC Timing - Absolute Specification . . . . . . . . . . . . . . . . . . . . . . . . 75
AC Timing Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Reference Load for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Slew Rate Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Output Slewrate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Input Slewrate - Differential signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Input Slewrate - Single ended signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Input and Data Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
TDDieemffiiinnniigttiiooDnnefffooinrritDDioaanttaafoSSreeInttuuppput((ttSDDSeS1)t)uaapnnd(dtIHSH)ooaldlnddTTiHmimoeeld((tTtDDiHmH)1,e)d,(iSftfIHien)rge.lne.t-i.Ea.ln.Dd.ea.dta. D.S.at.trao. b.Se.tsr.o.b..e..s..
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82
82
83
Slew Rate Definition for Input and Data Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Setup (tIS) and Hold (tIH) Time Derating Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Package Thermal Characterist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Sheet
5 Rev. 1.30, 2005-07
11222004-7N66-547B
5 Page 
HYB18T256161AF–[22/25/28/33] L[25/28/33]
256-Mbit DDR2 SGRAM
www.DataSheet4U.com
Overview
1.5 256Mbit DDR2 Addressing
Table 5 256 Mbit DDR2 Addressing
Configuration
Number of Banks
Bank Address
Auto-Precharge
Row Address
Column Address
Number of Column Address Bits
Number of I/Os
Page Size [Bytes]
16 x 16
4
BA[0:1]]
A10 / AP
A[12:0]
A[8:0]
9
16
1024 (1K)
Note
1.6 Input/Output Functional Description
Table 6 Input/Output Functional Description
Symbol
Type Function
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control inputs are
sampled on the crossing of the positive edge of CK and negative edge of CK. Output
(read) data is referenced to the crossing of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals
and device input buffers and output drivers. Taking CKE LOW provides Precharge
Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row
Active in any bank). CKE is synchronous for power down entry and exit and for self-
refresh entry. Input buffers excluding CKE are disabled during self-refresh. CKE is
used asynchronously to detect self-refresh exit condition. Self-refresh termination
itself is synchronous. After VREF has become stable during power-on and initialisation
sequence, it must be maintained for proper operation of the CKE receiver. For proper
self-refresh entry and exit, VREF must be maintained to this input. CKE must be
maintained HIGH throughout read and write accesses. Input buffers, excluding CK,
CK, ODT and CKE are disabled during power-down.
CS Input Chip Select: All commands are masked when CS is registered high. CS provides for
external rank selection on systems with multiple ranks. CS is considered part of the
command code.
ODT
Input
On Die Termination: ODT (registered high) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is applied to each DQ, UDQS, UDQS, LDQS,
LDQS, UDM and LDM signal. The ODT pin will be ignored if the EMRS(1) is
programmed to disable ODT.
RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being
entered
DM, LDM, UDM Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled high coincident with that input data during a Write access. DM is
sampled on both edges of DQS. Although DM pins are input only, the DM loading
matches the DQ and DQS loading. LDM and UDM are the input mask signals and
control the lower or upper bytes.
Data Sheet
11 Rev. 1.30, 2005-07
11222004-7N66-547B
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HYB18T256161AF-28.PDF ] | |
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