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LOGIC DEVICES - 24Mbit Frame Buffer/FIFO

Numéro de référence LF3324
Description 24Mbit Frame Buffer/FIFO
Fabricant LOGIC DEVICES 
Logo LOGIC DEVICES 





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LF3324 fiche technique
DEVICES INCORPORATED
LF3324
24Mbit Frame Buffer / FIFO
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Features
24,883,200-bit Frame Memory
74.25 Mhz Data Rate
May be Organized Into the Following Configurations:
• 3,110,400 x 8-bit
• 2,488,320 x 10-bit
• 2,073,600 x 12-bit
Operating Modes:
• Random Access with Burst Control
• FIFO
• Synchronous Shift Register
Near-Full/Empty Flags With Programmable
Thresholds
Flexible Pointer Manipulation
• Write and Read Pointers may be independently
jumped to arbitrary address locations
• Write or Read Pointers can be manipulated in real-
time based on external 24bit address
LF3324s may be Cascaded for depth and
width, supporting HDTV, Multiframe SDTV,
and other high resolution formats
• Seamless address space is maintained
with up to 8 cascaded devices
Built-in ITU-R BT.656 TRS detection and
Synchronization
Set & Clear Read/Write Pointer Control Pins
Choice of Control Interfaces:
• Two-wire Serial Microprocessor Interface
• Parallel Microprocessor Interface
Input Enable Control (Write Mask) for freeze-
frame applications
Output Enable Control (Data Skipping)
JTAG Boundary Scan - IEEE 1149.1
172 ball LBGA package
1.8V Internal Core Power Supply
3.3V I/O Supply
NOTE: This Preliminary Datasheet references LF3324BGC Engineering Samples
with an E marking under the part designation.
Applications
DTV/HDTV Video Stream Buffer
Frame Synchronization
CCTV Security Camera Systems
Time Base Correction (TBC)
Freeze-Frame Buffer
Regional Read/Write for Picture-in-Picture (PIP)
Field-Based or Frame-Based Comb Filtering
Video Capture & Editing Systems
Deep Data Buffering
Video Special Effects (Rotation, Zoom)
Test Pattern Generation
Motion Detection or Frame-to-Frame Correlation
LOGIC Devices Incorporated
Video Imaging Product
September 14, 2005 LDS.3324 E

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