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PDF K4S1G0632D Data sheet ( Hoja de datos )

Número de pieza K4S1G0632D
Descripción SDRAM stacked 1Gb D-die
Fabricantes Samsung Electronics 
Logotipo Samsung Electronics Logotipo



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No Preview Available ! K4S1G0632D Hoja de datos, Descripción, Manual

SDRAM stacked 1Gb D-die (x4, x8)
SDRAM
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stacked 1Gb D-die SDRAM Specification
54 TSOP-II with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 November. 2005

1 page




K4S1G0632D pdf
SDRAM stacked 1Gb D-die (x4, x8)
4.0 Package Physical Dimension
#54 #28
SDRAM
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0.25 TYP
0~8°C
#1
0.10 MAX
22.53 MAX
22.22 ± 0.10
#27
0.71
0.25~0.40
0.80
0.125+-00..007355
2.54 MAX
0.05 MIN
54Pin TSOP(II) Stack Package Dimension
5.0 Functional Block Diagram
CK,CK,CAS
RAS,WE,DM
CKE1,CS1
CKE0,CS0
128Mx4
128Mx4
DQ0 ~ DQ3
st.256Mb x 4
CK,CK,CAS
RAS,WE,DM
CKE1,CS1
A0-A12,
BA0,BA1
CKE0,CS0
64Mx8
64Mx8
DQ0 ~ DQ7
st.128Mb x 8
A0-A13,
BA0,BA1
Rev. 1.0 November. 2005

5 Page





K4S1G0632D arduino
SDRAM stacked 1Gb D-die (x4, x8)
SDRAM
15.0 AC Characteristics
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(AC operating conditions unless otherwise noted)
Parameter
Symbol
CLK cycle time
CAS latency=3
CAS latency=2
CLK to valid
output delay
CAS latency=3
CAS latency=2
Output data
hold time
CAS latency=3
CAS latency=2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold time
CLK to output in Low-Z
CLK to output
in Hi-Z
CAS latency=3
CAS latency=2
tCC
tSAC
tOH
tCH
tCL
tSS
tSH
tSLZ
tSHZ
75
Min Max
7.5
1000
10
5.4
6
3
3
2.5
2.5
1.5
0.8
1
5.4
6
Unit Note
ns 1
ns 1, 2
ns 2
ns 3
ns 3
ns 3
ns 3
ns 2
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
16.0 DQ Buffer Output Drive Characteristics
Parameter
Output rise time
Symbol
trh
Condition
Measure in linear
region : 1.2V ~ 1.8V
Min
1.37
Typ
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
1.30
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
Output fall time
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
Notes : 1. Rise time specification based on 0pF + 50 to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Max
4.37
3.8
5.6
5.0
Unit
Volts/ns
Volts/ns
Volts/ns
Volts/ns
Notes
3
3
1,2
1,2
Rev. 1.0 November. 2005

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