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PDF CBT3253A Data sheet ( Hoja de datos )
| Número de pieza | CBT3253A | |
| Descripción | Dual 1-of-4 FET multiplexer/demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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CBT3253A
www.DataSheet4U.com
Dual 1-of-4 FET multiplexer/demultiplexer
Rev. 01 — 24 October 2005
Product data sheet
1. General description
The CBT3253A is a dual 1-of-4 high-speed TTL-compatible FET
multiplexer/demultiplexer. The low on-resistance of the switch allows inputs to be
connected to outputs without adding propagation delay or generating additional ground
bounce noise.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
The CBT3253A is characterized for operation from −40 °C to +85 °C.
2. Features
s 5 Ω switch connection between two ports
s TTL-compatible input levels
s Minimal propagation delay through the switch
s ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
s Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
3. Ordering information
Table 1: Ordering information
Tamb = −40 °C to +85 °C
Type number Topside
mark
Package
Name
CBT3253AD CBT3253AD SO16
CBT3253ADB C3253A
SSOP16
CBT3253ADS CT3253A
SSOP16 [1]
CBT3253APW CT3253A TSSOP16
Description
Version
plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
plastic shrink small outline package;
16 leads; body width 5.3 mm
SOT338-1
plastic shrink small outline package;
16 leads; body width 3.9 mm;
lead pitch 0.635 mm
SOT519-1
plastic thin shrink small outline package; SOT403-1
16 leads; body width 4.4 mm
[1] Also known as QSOP16.
1 page  
Philips Semiconductors
CBT3253A
www.DataSheet4U.com
Dual 1-of-4 FET multiplexer/demultiplexer
9. Static characteristics
Table 6: Static characteristics
Tamb = −40 °C to +85 °C
Symbol Parameter
VIK
Vpass
ILI
ICC
input clamping voltage
pass voltage
input leakage current
quiescent supply current
∆ICC
Ci
Cio(off)
Ron
additional quiescent supply
current (control inputs)
input capacitance
(control pins)
off-state input/output
capacitance
ON-state resistance [3]
Conditions
VCC = 4.5 V; II = −18 mA
VI = VCC = 5.5 V; IO = −100 µA
VCC = 5 V; VI = 5.5 V or GND
VCC = 5.5 V; IO = 0 mA;
VI = VCC or GND
VCC = 5.5 V; one input at 3.4 V;
other inputs at VCC or GND
VI = 3 V or 0 V
A port; VO = 3 V or 0 V; OE = VCC
B port; VO = 3 V or 0 V; OE = VCC
VCC = 4.5 V; VI = 0 V; II = 64 mA
VCC = 4.5 V; VI = 0 V; II = 30 mA
VCC = 4.5 V; VI = 2.4 V; II = −15 mA
Min
-
3.4
-
-
[2] -
-
-
-
-
-
-
Typ [1]
-
3.6
-
-
Max
−1.2
3.9
±1
3
- 2.5
4.5 -
23.5 -
6.5 -
57
57
10 15
Unit
V
V
µA
µA
mA
pF
pF
pF
Ω
Ω
Ω
[1] All typical values are at VCC = 5 V, Tamb = 25 °C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
10. Dynamic characteristics
Table 7: Dynamic characteristics
VCC = +5.0 V ± 0.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
tPD
propagation delay from input (nA or nBn) to output (nBn or nA)
[1] -
-
0.25 ns
from input (Sn) to output (nA or nBn)
1.2 -
6.2 ns
ten
enable time [2]
from input (Sn) to output (nA or nBn)
1.3 -
6.3 ns
from input (nOE) to output (nA or nBn)
1.4 -
6.4 ns
tdis
disable time [3]
from input (Sn) to output (nA or nBn)
1.1 -
7.2 ns
from input (nOE) to output (nA or nBn)
1.0 -
7 ns
[1] The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
[2] Output enable time to HIGH and LOW level.
[3] Output disable time from HIGH and LOW level.
9397 750 12919
Product data sheet
Rev. 01 — 24 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 16
5 Page 
Philips Semiconductors
CBT3253A
www.DataSheet4U.com
Dual 1-of-4 FET multiplexer/demultiplexer
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
y
Z
16
9
c
EA
X
HE v M A
pin 1 index
1
e
8
wM
bp
A2
A1
Q
(A3)
A
Lp
L
detail X
θ
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
D (1) E (2)
e
5.1
4.9
4.5
4.3
0.65
HE
6.6
6.2
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT403-1
MO-153
L Lp Q v w y Z (1) θ
1
0.75 0.4
0.50 0.3
0.2 0.13 0.1
0.40
0.06
8o
0o
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 12. Package outline SOT403-1 (TSSOP16)
9397 750 12919
Product data sheet
Rev. 01 — 24 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 16
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