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PDF ADC1613D Data sheet ( Hoja de datos )
| Número de pieza | ADC1613D | |
| Descripción | Dual 16-bit ADC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ADC1613D series
www.DataSheet4U.com
Dual 16-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 02 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1613D is a dual-channel 16-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1613D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3.3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1613D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 72.5 dBFS; SFDR, 88 dBc
Sample rate up to 125 Msps
Clock input divider by 2 for less jitter
contribution
3 V, 1.8 V single supplies
Flexible input voltage range:
1 V to 2 V (peak-to-peak)
Two configurable serial outputs
INL ± 1 LSB; DNL ± 0.5 LSB
Pin compatible with the ADC1213D
series
HVQFN56 package
Input bandwidth, 600 MHz
Power dissipation, 995 mW at 80 Msps
SPI register programming
Duty cycle stabilizer
High IF capability
Offset binary, two’s complement, gray
code
Power-down mode and Sleep mode
Compliant with JESD204A serial
transmission standard
1 page  
NXP Semiconductors
ADC1613D series
www.DataSheet4U.com
ADC1613D series; serial JESD204A interface
Table 2. Pin description …continued
Symbol
Pin Type [1]
INBP
14 I
VDDA
15 P
VDDA
16 P
SCLK/DCS
17 I
SDIO/DCS
18 I/O
CS
AGND
RESET
SCRAMBLER
CFG0
CFG1
CFG2
CFG3
VDDD
DGND
DGND
DGND
VDDD
CMLPB
CMLNB
VDDD
DGND
DGND
VDDD
CMLNA
CMLPA
VDDD
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
SWING_0
SWING_1
DNC
VDDA
AGND
AGND
VDDA
19 I
20 G
21 I
22 I
23 I/O
24 I/O
25 I/O
26 I/O
27 P
28 G
29 G
30 G
31 P
32 O
33 O
34 P
35 G
36 G
37 P
38 O
39 O
40 P
41 G
42 G
43 I
44 I
45 G
46 P
47 I
48 I
49 O
50 P
51 G
52 G
53 P
Description
channel B analog input
analog power supply 3 V
analog power supply 3 V
SPI clock
data format select
SPI data IO
duty cycle stabilizer
chip select bar
analog ground
JEDEC digital IP reset
scrambler enable and disable
Table 29 (input) or OTRA (output)[2]
Table 29 (input) or OTRB (output)[2]
Table 29 (input)
Table 29 (input)
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
do not connect
analog power supply 3 V
analog ground
analog ground
analog power supply 3 V
ADC1613D_SER_2
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 43
5 Page 
Table 6.
Symbol
IMD
αct(ch)
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Characteristics …continued
Parameter
Conditions
ADC1613D065
ADC1613D080
ADC1613D105
ADC1613D125
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
intermodulation
distortion
channel crosstalk
fi = 3 MHz
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
fi = 70 MHz
- 89 - - 89 - - 88 - - 89 - dBc
- 88 - - 88 - - 88 - - 88 - dBc
- 87 - - 87 - - 86 - - 86 - dBc
- 84 - - 85 - - 83 - - 84 - dBc
- 100 - - 100 - - 100 - - 100 - dBc
[1] Typical values measured at VDDA = 3 V, VDDD = 1.8 V, Tamb = 25 °C. Minimum and maximum values are across the full temperature range Tamb = −40 °C to +85 °C at VDDA = 3 V,
VDDD = 1.8 V; VI (INAP, INBP) − VI (INAM, INBM) = −1 dBFS; internal reference mode; 100 Ω differential applied to serial outputs; unless otherwise specified.
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet ADC1613D.PDF ] | |
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