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PDF ADC1415S Data sheet ( Hoja de datos )
| Número de pieza | ADC1415S | |
| Descripción | Single 14-bit ADC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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ADC1415S series
www.DataSheet4U.com
Single 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
with input buffer; CMOS or LVDS DDR digital outputs
Rev. 03 — 12 April 2010
Preliminary data sheet
1. General description
The ADC1415S is a single channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1415S is accurate
enough to guarantee zero missing codes over the entire operating range. Supplied from a
single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,
thanks to a separate digital output supply.
The ADC1415S supports the Low Voltage Differential Signalling (LVDS) Double Data
Rate (DDR) output standard. An integrated Serial Peripheral Interface (SPI) allows the
user to easily configure the ADC.
The device also includes a SPI programmable full-scale to allow flexible input voltage
range from 1 V to 2 V (peak-to-peak). With excellent dynamic performance from the
baseband to input frequencies of 170 MHz or more, the ADC1415S is ideal for use in
communications, imaging and medical applications - especially in high Intermediate
Frequency (IF) applications thanks to the integrated input buffer. The input buffer ensures
that the input impedance remains constant and low and the performance consistent over
a wide frequency range.
2. Features and benefits
SNR, 72 dBFS / SFDR, 86 dBc
Input bandwidth, 600 MHz
Sample rate up to 125 Msps
Power dissipation, 635 mW at 80 Msps,
including analog input buffer
14-bit pipelined ADC core
SPI
Clock input divider by 2 for less jitter Duty cycle stabilizer
contribution
Integrated input buffer
Fast OuT of Range (OTR) detection
Flexible input voltage range: 1 V (p-p) to INL ±1.5 LSB, DNL ±0.5 LSB
2 V (p-p)
CMOS or LVDS DDR digital outputs Offset binary, two’s complement, gray
code
Pin compatible with the ADC1215S
Power-down and Sleep modes
series, ADC1015S series and the
ADC1115S125
HVQFN40 package
1 page  
NXP Semiconductors
ADC1415S series
www.DataSheet4U.com
ADC1415S series; input buffer; CMOS or LVDS DDR digital outputs
Table 2. Pin description (CMOS digital outputs)
Symbol
Pin Type [1]
Description
D13 17 O
data output bit 13 (MSB)
D12 18 O
data output bit 12
D11 19 O
data output bit 11
D10 20 O
data output bit10
D9 21 O
data output bit 9
D8 22 O
data output bit 8
D7 23 O
data output bit 7
D6 24 O
data output bit 6
D5 25 O
data output bit 5
D4 26 O
data output bit 4
D3 27 O
data output bit 3
D2 28 O
data output bit 2
D1 29 O
data output bit 1
D0 30 O
data output bit 0 (LSB)
DAV 31 O
data valid output clock
n.c. 32 -
not connected
VDDO
33 P
output power supply
OGND
34 G
output ground
OTR
35 O
out of range
SCLK/DFS 36
I
SPI clock / data format select
SDIO/ODS 37
I/O
SPI data IO / output data standard
CS 38 I
SPI chip select
SENSE
39 I
reference programming pin
VREF
40 I/O
voltage reference input/output
[1] P: power supply; G: ground; I: input; O: output; I/O: input/output.
Table 3. Pin description (LVDS/DDR) digital outputs)
Symbol
Pin [1] Type [2] Description
D12_D13_M 17 O differential output data D12 and D13 multiplexed, complement
D12_D13_P 18 O differential output data D12 and D13 multiplexed, true
D10_D11_M 19 O differential output data D10 and D11 multiplexed, complement
D10_D11_P 20 O differential output data D10 and D11 multiplexed, true
D8_D9_M 21 O differential output data D8 and D9 multiplexed, complement
D8_D9_P 22 O differential output data D8 and D9 multiplexed, true
D6_D7_M 23 O differential output data D6 and D7 multiplexed, complement
D6_D7_P 24 O differential output data D6 and D7 multiplexed, true
D4_D5_M 25 O differential output data D4 and D5 multiplexed, complement
D4_D5_P 26 O differential output data D4 and D5 multiplexed, true
D2_D3_M 27 O differential output data D2 and D3 multiplexed, complement
D2_D3_P 28 O differential output data D2 and D3 multiplexed, true
D0_D1_M 29 O differential output data D0 and D1 multiplexed, complement
ADC1415S_SER_3
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 12 April 2010
© NXP B.V. 2010. All rights reserved.
5 of 39
5 Page 
Table 7.
Symbol
IMD
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Dynamic characteristics[1] …continued
Parameter
Conditions
ADC1415S065
ADC1415S080
ADC1415S105
ADC1415S125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Intermodul-
ation distortion
fi = 3 MHz
fi = 30 MHz
fi = 70 MHz
fi = 170 MHz
- 89 - - 89 - - 88 - - 89 - dBc
- 88 - - 88 - - 88 - - 88 - dBc
- 87 - - 87 - - 86 - - 86 - dBc
- 84 - - 85 - - 83 - - 84 - dBc
[1] Typical values measured at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V; Tamb = 25 °C and CL = 5 pF; minimum and maximum values are across the full temperature range
Tamb = −40 °C to +85 °C at VDDA(3V) = 3 V, VDDO = 1.8 V, VDDA(5V) = 5 V, VINP − VINM = −1 dBFS; internal reference mode; applied to CMOS and LVDS interface; unless otherwise
specified.
11 Page | ||
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| PDF Descargar | [ Datasheet ADC1415S.PDF ] | |
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