PDF ADC0808S250 Data sheet ( Hoja de datos )

Número de pieza	ADC0808S250
Descripción	(ADC0808S125 / ADC0808S250) Single 8-bit ADC
Fabricantes	NXP Semiconductors
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No Preview Available ! ADC0808S125/250 www.DataSheet4U.com Single 8-bit ADC, up to 125 MHz or 250 MHz Rev. 03 — 24 February 2009 Product data sheet 1. General description The ADC0808S is a differential, high-speed, 8-bit Analog-to-Digital Converter (ADC) optimized for telecommunication transmission control systems and tape drive applications. It allows signal sampling frequencies up to 250 MHz. The ADC0808S clock inputs are selectable between 1.8 V Complementary Metal Oxide Semiconductor (CMOS) or Low-Voltage Differential Signals (LVDS). The data output signal levels are 1.8 V CMOS. All static digital inputs (CLKSEL, CCSSEL, CE_N, OTC, DEL0 and DEL1) are 1.8 V CMOS compatible. The ADC0808S offers the most ﬂexible acquisition control system possible due to its programmable Complete Conversion Signal (CCS) which allows the delay time of the acquisition clock and acquisition clock frequency to be adjusted. The ADC0808S is supplied in an HTQFP48 package. 2. Features I 8-bit resolution I High-speed sampling rate up to 250 MHz I Maximum analog input frequency up to 560 MHz I Programmable acquisition output clock (complete conversion signal) I Differential analog input I Integrated voltage regulator or external control for analog input full-scale I Integrated voltage regulator for input common-mode reference I Selectable 1.8 V CMOS or LVDS clock input I 1.8 V CMOS digital outputs I 1.8 V CMOS compatible static digital inputs I Binary or 2’s complement CMOS outputs I Only 2 clock cycles latency I Industrial temperature range from −40 °C to +85 °C I HTQFP48 package 3. Applications I 2.5G and 3G cellular base infrastructure radio transceivers I Wireless access systems I Fixed telecommunications 1 page NXP Semiconductors ADC0808S125/250 www.DataSheet4U.com Single 8-bit ADC, up to 125 MHz or 250 MHz Table 3. Pin type description Type Description I input O output I(CMOS) 1.8 V CMOS level input O(CMOS) 1.8 V CMOS level output P power supply G ground 7. Functional description 7.1 CMOS/LVDS clock input The circuit has two clock inputs CLK+ and CLK−, with two modes of operation: • LVDS mode: CLK+ and CLK− inputs are at differential LVDS levels. An external resistor of between 80 Ω and 120 Ω is required; see Figure 3. VO(dif) undefined state maximum Vidth minimum Vidth LVDS DRIVER RECEIVER CLK+ Vgpd CLK− 001aah720 Fig 3. LVDS clock input • 1.8 V CMOS mode: CLK+ input is at 1.8 V CMOS level and sampling is done on the rising edge of the clock input signal. In this case pin CLK− must be grounded; see Figure 4. CMOS DRIVER CLK+ CLK− Fig 4. CMOS clock input 001aai272 ADC0808S125_ADC0808S250_3 Product data sheet Rev. 03 — 24 February 2009 © NXP B.V. 2009. All rights reserved. 5 of 23 5 Page NXP Semiconductors ADC0808S125/250 www.DataSheet4U.com Single 8-bit ADC, up to 125 MHz or 250 MHz Table 12. Static characteristics …continued VCCA = 3.0 V to 3.6 V; VCCD = 1.65 V to 1.95 V; VCCO = 1.65 V to 1.95 V; pins AGND1, AGND2 and DGND1 shorted together; Tamb = −40 °C to +85 °C; Vi(IN) − Vi(INN) = 2.0 V − 0.5 dB; VI(cm) = 0.95 V; VFSIN = 0 V; typical values are measured at VCCA = 3.3 V, VCCD = VCCO = 1.8 V, Tamb = 25 °C and CL = 10 pF; unless otherwise speciﬁed. Symbol Parameter Conditions Min Typ Max Unit Vidth input differential threshold voltage \|Vgpd\| < 50 mV II input current 825 mV < VI < 1575 mV 1.8 V CMOS clock input; see Figure 4 [2] −100 - +100 mV - - 50 µA VIL LOW-level input voltage VIH HIGH-level input voltage IIL LOW-level input current IIH HIGH-level input current Analog inputs: pins IN and INN VIL = 0.2VCCD VIH = 0.8VCCD DGND 0.8VCCD - - - - - - 0.2VCCD VCCD 50 50 V V µA µA Ri Ci VI(cm) input resistance input capacitance common-mode input voltage Vi(IN) = Vi(INN); output code = 127 [1] - [1] - 0.7 1.0 - 1.0 - 0.95 1.0 MΩ pF V Digital input pins: OTC, CE_N, DEL0, DEL1, CLKSEL and CCSSEL VIL LOW-level input voltage VIH HIGH-level input voltage IIL LOW-level input current VIL = 0.3VCCD IIH HIGH-level input current VIH = 0.7VCCD Voltage controlled regulator output: pin CMADC DGND 0.8VCCD - - - - - - 0.2VCCD VCCD 50 50 V V µA µA VO(cm) common-mode output voltage Reference voltage input: pin FSIN[3] 0.85 0.95 1.1 V VFSIN voltage on pin FSIN internal reference external reference - 0 0.6 V 1.15 1.25 1.35 V Ii(FSIN) input current on pin FSIN Vi(p-p)(max) maximum peak-to-peak input voltage internal reference external reference - 12 - µA 1.92 2 2.03 V Digital outputs: pins D0 to D7, CCS and IR VFSIN = 1.15 V VFSIN = 1.25 V VFSIN = 1.35 V 1.80 1.825 1.85 V 1.98 1.99 2.03 V 2.11 2.16 2.18 V VOL LOW-level output voltage VOH HIGH-level output voltage OGND - VCCO − 0.2 - 0.2 VCCO V V [1] Guaranteed by design. [2] \|Vgpd\| is the voltage of ground potential difference across or between boards. [3] The ADC input range can be adjusted with an external reference voltage applied to pin FSIN. This voltage must be referenced to AGND. ADC0808S125_ADC0808S250_3 Product data sheet Rev. 03 — 24 February 2009 © NXP B.V. 2009. All rights reserved. 11 of 23 11 Page

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