PDF K7D323674A Data sheet ( Hoja de datos )

Número de pieza	K7D323674A
Descripción	1Mx36 & 2Mx18 SRAM
Fabricantes	Samsung Electronics
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No Preview Available ! K7D323674A K7D321874A Advance 1Mx36 & 2Mx1w8wwS.DRatAaShMeet4U.com Document Title 32M DDR SYNCHRONOUS SRAM Revision History Rev No. History DraftData Remark Rev. 0.0 Initial document. Dec. 2002 Advance Rev. 0.1 Remove /G operation thru the Spec. - Remove /G from PUNCTIONAL BLOCK DIAGRAM, PIN CONFIGURA- TION, TRUTH TABLE and TIMING WAVEFORMs Jan. 2003 Advance Add 300MHz Speed bin. - Add Part ID at ORDERING INFORMATION & I DD30 at DC CHARACTERIS- TICS Change ILI and ILo at DC CHARCATERISTICS - ILI : MIN -1 -> -3, MAX 1 -> 3, ILo : MIN -1 -> -5, MAX 1 -> 5 Change the comment of Programmable Impedance Output Driver. Change RECOMMENDED DC OPERATING CONDITIONS. PRE- PUBLICATION DRAFT- VREF : Min 0.68 -> 0.65, Max 1.0 -> 0.85 SUBJECT TO CHANGE WITHOUT NOTICEChange PIN CAPACITANCE : CIN: 3 -> 3.1 Change AC TEST CONDITIONS : TR/R F: 0.4/0.4 -> 0.5/0.5 Change AC TIMING CHARACTERISTICS - tCHCL : tKHKL -0.1 -> tKHKL -0.2 , tCLCH : tKLKH -0.1 -> tKLKH -0.2 - tCXCV : 2.10 -> 2.30 Rev 0.2 Change VDDQ RANGE - In FEATURES : 1.5V VDDQ -> 1.5~.1.8V VDDQ - In RECOMENDED DC OPERATING CONDITIONS : Max VDDQ : 1.6 -> 1.9 Feb. 2003 Advance Change TRUTH TABLE : Remove Clock Stop Change DC CHARACTERISTICS - x36 IDD : IDD50 : 950 -> 1050, IDD45 : 850 -> 950, IDD40: 800 -> 860, IDD30: 750 -> 760 - x18 IDD: IDD50 : 850 -> 1000, IDD45 : 800 -> 900, IDD40: 750 -> 810, IDD30: 700 -> 710 - ISB1 : 150 -> 200 Change PIN CAPACITANCE : CIN : 3.1 -> 3.2, C OUT : 4 -> 4.2 Change AC TIMING CHARACTERISTICS - MIN tKHKL, tKHKL : -40 : 1.1 -> 1.2, -30 : 1.1 -> 1.4 - MIN tAVKH, tBVKH, tKHAX, tKHBX : -45 : 0.25 -> 0.27 - tKXCV MIN/MAX : 0.8/2.3 -> 1.0/2.5 Change PACKAGE THERMAL CHARACTERISTICS The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquart ers. -1- Rev 0.4 Jun. 2003 1 page K7D323674A K7D321874A Advance 1Mx36 & 2Mx1w8wwS.DRataAShMeet4U.com PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7D323674A(1Mx36) 1234 A VSS VDDQ SA SA B D Q20 D Q19 SA VSS C VSS VDDQ SA SA D D Q30 D Q28 SA V ss(5) E VSS VDDQ VSS VDD F D Q21 CQ DQ 18 VDD G VSS VDDQ VSS VSS H D Q31 D Q29 DQ 27 VDD J VSS VDDQ VSS VDD K D Q22 D Q24 DQ 26 VSS L VSS VDDQ VSS LBO (7) M D Q32 CQ DQ 35 VDD N VSS VDDQ VSS VDD P D Q23 D Q25 NC * VSS R VSS VDDQ V DD(4) SA T D Q33 D Q34 SA VSS U VSS VDDQ TMS TDI 5 ZQ B1 SA VDD VREF VDD K K VDD B2 B3 VDD VREF VDD(2) SA 1 SA 0 TCK 6 SA VSS SA Vss(6) VDD VDD VSS VDD VDD VSS MODE(9) VDD VDD VSS SA VSS TDO 7 SA SA SA SA VSS D Q17 VSS DQ 8 VSS DQ 9 VSS DQ 0 VSS SA VDD(3) SA NC(8) K7D321874A(2Mx18) 1234 A VSS VDDQ SA SA B NC D Q10 SA VSS C VSS VDDQ SA SA D D Q11 NC SA V ss(5) E VSS VDDQ V SS VDD F NC CQ NC VDD G VSS VDDQ V SS VSS H D Q12 NC D Q9 VDD J VSS VDDQ V SS VDD K NC D Q15 NC VSS L VSS VDDQ V SS LBO(7) M D Q13 NC DQ 17 VDD N VSS VDDQ V SS VDD P NC D Q16 SA VSS R VSS VDDQ V DD(4) SA T D Q14 NC SA VSS U VSS VDDQ TMS TDI (1) Variable address see "Variable address assignment table" (2) Variable address see "Variable address assignment table" (3) Variable address see "Variable address assignment table" (4) Variable address see "Variable address assignment table" (5) Variable address see "Variable address assignment table" (6) Variable address see "Variable address assignment table" (7) LBO for DDR1, M 2 for DDR3 (8) NC for DDR1, ZT for DDR3 (9) Internally NC since DDR2 is not supported 5 ZQ B1 SA V DD VREF V DD K K V DD B2 B3 V DD VREF VDD(2) SA 1 SA 0 TCK 6 SA VSS SA Vss(6) VDD VDD VSS VDD VDD VSS MODE(9) VDD VDD VSS SA VSS TDO 7 SA SA SA SA VSS DQ 8 VSS NC VSS DQ 0 VSS NC VSS SA V DD(3) SA NC(8) -5- 8 VDDQ DQ 16 VDDQ D Q7 VDDQ CQ VDDQ D Q6 VDDQ DQ 11 VDDQ CQ VDDQ DQ 10 VDDQ D Q1 VDDQ 8 VDDQ NC VDDQ D Q7 VDDQ NC VDDQ D Q6 VDDQ NC VDDQ CQ VDDQ NC VDDQ D Q1 VDDQ 9 VSS D Q15 VSS D Q5 VSS D Q14 VSS D Q4 VSS D Q13 VSS D Q3 VSS D Q12 VSS D Q2 VSS 9 VSS D Q5 VSS NC VSS D Q4 VSS NC VSS D Q3 VSS NC VSS D Q2 VSS NC VSS Rev 0.4 Jun. 2003 5 Page K7D323674A K7D321874A Advance 1Mx36 & 2Mx1w8wwS.DRatAaSMheet4U.com PIN CAPACITANCE Parameter Symbol Input Capacitance C IN Data Output Capacitance C OUT NOTE : Periodically sampled and not 100% tested.(TA=25°C, f=500MHz) Test Condition VIN=0V VOUT=0V TYP - - AC TEST CONDITIONS (TA=0 to 70°C, VDD=2.37 -2.63V, VDDQ=1.5V) Parameter Input High/Low Level Input Reference Level Input Rise/Fall Time Output Timing Reference Level Clock Input Timing Reference Level Output Load Symbol VIH/VIL VREF T R/TF Value 1.25/0.25 0.75 0.5/0.5 0.75 Cross Point See Below AC TEST OUTPUT LOAD Max 3.2 4.2 Unit V V ns V V 25Ω DQ 50Ω 5pF 0.75V 50Ω 5pF 50Ω 50Ω 0.75V 0.75V Unit pF pF Note - - - - - - - 11 Rev 0.4 Jun. 2003 11 Page

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